Hello, I want to use the LMK as a supply clock for a JESD204B connection. I'd like to supply it with a 120 MHz clock at CLKin1, and output 120 MHz, 30 MHz, and 10 MHz. If I set the clock dividers (registers 0x108 and 0x120 in this case) to 0x4 and 0xC, I get the correct division for the 30 MHz and 10 MHz outputs.
However if I try to set Register 0x100 to 0x01 to pass through the 120 MHz signal as is, the signal is actually divided by 32. There appears to be no difference between a register value of 0x0 (nominally divide by 32) and 0x1 (supposed to be divide by 1, but is actually divide by 32). I see this effect on the other CLKoutX_DIV registers (0x108 and 0x120). Setting the value to 0x1 means that the clock is divided by 32 rather than passed through with its original frequency.
Is this the intended functionality? How do I pass through a CLKin1 to any of the outputs with NO division?
