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CDCE6214: Please advice register setting

Hironori Yoshimura
Intellectual 1851 points

Part Number: CDCE6214
Other Parts Discussed in Thread: TICSPRO-SW,

Dear CTS Team,  I need your help.

Please kindly advice how to set-up internal register setting ?  I am reviewing datasheet but it is very complicated for me.

Output:

　OUT0 Output：13.500MHz　LVCMOS

　OUT4_P Output：13.500MHz　LVCMOS

Input:  it depended on the external circuit exchanging together then input into preref input.

    Case 1 PREREF_P Input 74.250 MHz   LVCMOS　Clock rate: 2/11
    or Case 2 PREREF_P Input  LVCMOS　clock rate: 91/500

Please also advice un-used pins following.

　PREREF_N input: Pull-down
   SECREF_P,N   Input
   OUT1,2,3_P,N  Output
   OUT4_N  Output

  • 0
    TI__Mastermind 35320 points

    Hello Yoshimura-san,

    Please take a look at TICS Pro programming software (TICSPRO-SW), which has a device profile for the CDCE6214-Q1 (works the same as CDCE6214). TICS Pro provides a GUI to help clarify the function and purpose of different register settings, and can be used to program the device EVM for testing different configurations.

    OUT0 can only generate an output from the reference clock. 13.5MHz is not an integer divide of 74.25MHz, so OUT0 cannot generate the 13.5MHz clock. You could instead generate the 13.5MHz from OUT1.

    The least common multiple of 74.25MHz and 13.5MHz is 148.5MHz, so the VCO frequency must be an integer multiple of 148.5MHz. The VCO range is 2335MHz to 2625MHz, so one valid option is 148.5MHz * 16 = 2376MHz. We can set the R-divider = 1, the N-divider = 32, and the total output divide is 2376/13.5 = 176, which can be factored to 4 (PSA) and 44 (CHDIV).

    Unused pins:

    • PRIREF_N: short to GND
    • SECREF: leave floating, can be disabled in software
    • Output pins: leave floating, can be disabled in software

    Regards,

  • 0 in reply to Derek Payne
    TI__Intellectual 1851 points

    I missed Case2 FREQ option. please kindly advice below case as well?
    I have successfully installed TCSpro as below.  Would you please advice in case of below?

    Case 2 requirement:
     PREREF_P  74.250/1.001 (==74,1758) MHz  LVCMOS    
     OUT1/OUT4 : 13.5MHz  LVCMOS  Clock rate: 91/500

  • 0 in reply to Hironori Yoshimura
    TI__Mastermind 35320 points

    Hello Yoshimura-san,

    Apologies for the delay. The setup is mostly the same for case 2, but with the fractional divider set to 32/1000 (simplifies to 4/125) and the PLL Order set to fractional (I recommend first order).

    Regards,