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LMX2571: Single ended input

Hirotaka Matsumoto
Guru 27585 points
Part Number: LMX2571
Other Parts Discussed in Thread: LMK03328

Hi all

Would you mind if we ask LMX2571?
We would like to confirm Voscin with Single ended input condtion.

<Question1>
How much is the VIL?
We assume that there is only the description of VIH, min=1.4V and max=3.3V.

<Question2>
On 6.5 Electrical Characteristics, there is the description Vosin's the condition with Single ended input.
Could you share us the test condtion for this as the reference?
Is input CMOS? 

<Question3>
In relation to Question2, if the input reference is CMOS in case of test circuit, why is the min=1.4V?
We guess that it will be VCC×0.7.

Kind regards,

Hirotaka Matsumoto

  • 0
    TI__Guru** 107300 points

    Hi Matsumoto-san,

    The datasheet is design in the way that single-ended input means CMOS input, that's why the min. VIL is 1.4V. In fact, with single-ended input buffer setting, we could DC-couple a single-ended reference clock signal with min. voltage swing of 300mV.

    If you have a TCXO reference clock with 0.8V voltage swing, there is no issue to connect it to the OSCin pin directly with single-ended buffer configuration.

  • 0 in reply to Noel Fung
    Guru 27585 points

    Noel san

    Thank you for your reply!

    The datasheet is design in the way that single-ended input means CMOS input, that's why the min. VIL is 1.4V.
    ->Is "VIL is 1.4V" typo? We assume that 1.4V means VIH's minimum, right?
    　If our recognition is correct, how much is the VIL?

    Kind regards,

    Hirotaka Matsumoto


  • 0 in reply to Hirotaka Matsumoto
    TI__Guru** 107300 points

    Hi Matsumoto-san,

    Sorry for the confusion, it was a typo, it should be min. VIH = 1.4V. 

    In fact, VIH and VIL are not the right terms to describe the input voltage specification. What we care is the input voltage swing (Vosc) rather than the crest and trough voltage.

  • 0 in reply to Noel Fung
    Guru 27585 points

    Noel san

    Thank you for your reply!

    n fact, VIH and VIL are not the right terms to describe the input voltage specification. 
    ->We mentioned Single-ended input. So, in case of single-ended input with LVCMOS, we assume that there is the VIL condtion like as LMK03328.
       Could you share us your recognition?


    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    TI__Guru** 107300 points

    Hi Matsumoto-san,

    right, for CMOS input, VIH an VIL are the appropriate terms to describe the specification.

    Single-ended signal could be anything (for example, a sine wave; the signal on one of the LVDS output pins; a CMOS, etc.). So, in my opinion, when we define a single-ended input signal specification, we should simply define the voltage swing, unless we have requirement on the DC content of the signal. 

  • 0 in reply to Noel Fung
    Prodigy 20 points

    Noel san

     

    Please allow me to get into this transaction.

    Your answer is strange to me.

    Referring to the internal circuit model of OSC input of the LMX2571 on E2E forum,

    In Single end mode, input is connected to a comparator without DC block capacitor.

    This means that SCI input may be compared with threshold reference.

    So, absolute voltage level, rather than voltage swing, is critical.

     

    If my though is incorrect, can you let me know how the device determine the signal

    Level High and Low, in Single end DC coupling mode.

     

    https://e2e.ti.com/support/clock-and-timing/f/48/p/966933/3574965?tisearch=e2e-sitesearch&keymatch=LMX2571#3574965

     

    Mita

  • 0 in reply to Kikuo MIta
    TI__Guru** 107300 points

    Hi Matsumoto-san,

    The simplified diagram wasn't detailed enough, there are DC-blocking capacitors inside the SE receiver, that's why the DC content of the input signal is not matter.

  • 0 in reply to Noel Fung
    Expert 2345 points

    Thanks.

    I understand it.

    Mita