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CDCLVD1208 - single ended use case and understanding datasheet jitter spec.

Anjli Behl
Prodigy 715 points
Other Parts Discussed in Thread: CDCLVD1208

RE: CDCLVD1208 questions

1) I am not using the differential input 0, should I connect the inputs as follows:

INP0  -  1K pull-up to 2.5V supply rail ?

INN0 -  1K pull-down to ground?

2) The spec mentions ”low additive jitter:  < 300 fs RMS in 10 KHz to 20 MHz”

I will use the chip with a 125.0MHz clock and a 312.50MHz clock and I need to know what kind of additive jitter I can expect at each of these rates?

The answer I got was:

The  additive jitter spec is valid up to 800 MHz

You will get <300 fs additive jitter (from 10k-20MHz) with your applications frequencies 125 MHz and 312.5 MHz.

 

I want to know how much jitter the device is going to add at 125.0MHz and 312.50MHz which are the two clock rates I am going to operate the part at.

I will use one part for 125.0 Mhz and another part for 312.50 MHz to feed the reference clocks of an FPGA.

The way the spec is written “<300 fs additive jitter from 10k-20MHz” does it mean there is no jitter generated by the part above 20MHz?

  • TI__Expert 4585 points

    Hi Anjli,

    Here are my comments

    1. We have added recommendation for unused inputs into the datasheet (page 14).                                                                                                                                                             "For unused input, it is recommended to ground both input pins (INP, INN) using 1 kΩ  resistors."

    2.  The maximun additive jitter is 300 fs  up to 800 Mhz applications frequency.  For 125 MHz and 312.5 MHz clock frequency max spec is same. I can guess the typical values at these two frequencys ( max spec remains same) based on our experience.

    125 MHz - typical additive jiiter will be < 175 fs

    312.5 MHz  - typical additive jiiter will be < 150fs

    The way the spec is written “<300 fs additive jitter from 10k-20MHz” does it mean there is no jitter generated by the part above 20MHz?

    No, it does not mean that. We chose  10kHz to 20 MHz integration rage as a standard (other vendors do the same). If you integrate beyond 20 MHz, it will add more jitter. You can see the phase noise measurement example at page 7 of the datasheet.

     

    Thanks,

    Firoj