LMK04832: SYSREF synchronization

Hi Liam,

Just so you know, the LMK04832 requires external loop filter components to operate correctly; if the external loop filter components are not used, the PLL will be unstable and will probably not lock. We have a tool called PLLatinum Sim (PLLATINUMSIM-SW) which helps to determine the optimal loop filter parameters.

As far as the multiple devices question, I meant "do you have two or more LMK04832 which need to have their outputs phase-synchronized in the same system", and it sounds like the answer is no. I'll assume you are just synchronizing the one device unless you tell me otherwise.

Switching a CLKout from device clock to SYSREF (i.e. changing CLKout#_SRC_MUX) should not impact the phase of the clock, and therefore should not require a resynchronization. However, if the divider values are changed to produce a different device clock or SYSREF frequency, a new synchronization must be performed.

Now, for the SYNC procedure. I included a little background on the device architecture so that the operations being performed are better contextualized. I also included some steps which are optional - I realize you asked for the simplest SYNC sequence, but since the optional steps can sometimes have implications for the system (e.g. unexpected SYSREF pulses during synchronization), I prefer to explain the options and let you decide if you want to implement them.

The SYNC and the SYSREF subsystems share the same distribution path in the device (referred to in the datasheet as the "SYSREF distribution path"). There are several bits (SYNC_DIS0, SYNC_DIS2, ..., SYNC_DIS12, SYNC_DISSYSREF) which gate the SYSREF distribution path to each divider's reset input when set, and which permit reset when cleared. During synchronization, since the SYNC pulse is on the SYSREF distribution path, any outputs configured to produce SYSREF will also output the SYNC pulse unless they are pre-configured to a mute state during the SYNC event. The SCLKx_y_DIS_MODE registers and the SYSREF_GBL_PD bit can be used to selectively mute SYSREF outputs.

Each SYSREF path in the channels (output pairs, e.g. 0_1, 2_3) includes a local delay, SCLKx_y_DDLY. This delay can be bypassed, or set to some value between 1.5-11 VCO cycles. We typically recommend using the local delays (even if it is not strictly required) because the local delays act as a retiming stage next to the divider in the channel, ensuring the phase alignment between device clocks and SYSREFs is more precise. If the local delays are bypassed, the internal propagation delay between the SYSREF divider stage and the output configured for SYSREF determines part of the phase alignment; this propagation delay could be susceptible to skew over temperature or supply voltage. If the SYSREF local digital delays are used, the delay counters must be cleared before synchronization by setting the SYSREF_CLR bit for at least 15 VCO cycles.

The synchronization procedure for the one-device, PLL2-only case is as follows:

1. (Optional) To mute the SYSREF outputs during synchronization, configure the applicable SCLKx_y_DIS_MODE for the outputs you wish to mute. Typically this looks like configuring for conditional low or conditional VCM, followed by setting SYSREF_GBL_PD=1 to prevent pulses from SYSREF outputs during the SYNC event. Alternately, there is a VCM option which applies the common-mode voltage to the output, regardless of the state of SYSREF_GBL_PD.
2. Enable the device clock digital delays (DCLKx_y_DDLY_PD=0, SYSREF_DDLY_PD=0) for applicable clocks. Program the digital delay values (DCLKx_y_DDLY, SYSREF_DDLY) to align device clocks to SYSREFs. More information about the digital delay settings can be found in the LMK04832 datasheet, section 8.3.5.
3. Configure SYNC_MODE=1 (SYNC pin), SYSREF_MUX=0 (Normal SYNC).
4. Set SYNC_DISx=0 for applicable clocks. For example, if CLKout0,1,2 are used, and CLKout1 will be SYSREF, you would set SYNC_DIS0=0, SYNC_DIS2=0, and SYNC_DISSYSREF=0.
5. (Optional, if SCLKx_y_DDLY != 0) Set SYSREF_CLR=1 for at least 15 clock distribution path cycles (VCO cycles), then back to 0. In PLL2-only use case, this will be complete in less than one SPI transaction. If SYSREF local digital delay is not used, this step can be skipped.
6. Toggle the SYNC pin, or from software toggle SYNC_POL state between inverted and not inverted. This generates the SYNC pulse and resets the dividers. If you use an external signal on the SYNC pin instead of toggling SYNC_POL, make sure that SYSREF_REQ_EN=0 so that the SYSREF_MUX does not shift into continuous SYSREF mode.
7. Set all SYNC_DISx=1, including SYNC_DISSYSREF.
8. Restore the state of SYNC_MODE and SYSREF_MUX to the desired values.
9. (Optional) if SCLKx_y_DIS_MODE was used to mute SYSREF outputs during the SYNC event, restore SCLKx_y_DIS_MODE=0 for active state, or set SYSREF_GBL_PD=0 if SCLKx_y_DIS_MODE is set to a conditional option.
10. (Optional) To reduce power consumption, after the synchronization event is complete, DCLKx_y_DDLY_PD=1 and SYSREF_DDLY_PD=1 disable the digital delay counters (which are only used immediately after the SYNC pulse to delay the output by some number of VCO counts).

For more information, see the datasheet section 8.3.1 through 8.3.5.

Regards,