LMX2571: lock detect issue.

Hi Maynard,

I don't know how I can help you with the information you provided. Could you get some synthesizer related information for us to guess?

The synthesizer has some memory to keep the configuration as long as Vcc is maintained. A Vcc power up will trigger the internal POR to reset all the register settings to silicon default.

Hi Noel, 

Good day, I just received reply from customer. For me to now miss any information. I'll copy the reply below.

" I am living lmx2571njkrt lock issue , synthesizer have 3 statement(please see picture) when ı power up and power down each time
how can ı fix that lock status problem?

According to software(mux out pin 10. pin of IC ) lockdet a or lock det b should be high but there is a 3 statement

1- LOCDET A =3.3 VOLT and LOCDET B =3.3 VOLT(this is abnormal)
2-LOCDET A =3.3 VOLT and LOCDET B =0VOLT( this is normal but not always like this )
3-LOCDET A =0 VOLT and LOCDET B =3.3 VOLT ( this is normal but more less than statement 2)
So the question why mux out 10. pins is looking high on two lmx2571 (statement -1 )?

how can ı fix that lock issues problem

"

According to customer, there is no more information they can add.

Regards,

Maynard.

Hi Maynard,

I am not interested in how their product is operated, I want to know how they operate our product - LMX2571. If I do not have any information regrading the operation of LMX2571, I am not able to help resolve their issue.

Please help get both the hardware and software configuration of LMX2571, thank you.

Hi Noel, 

Regarding the schematic and code used by the customer, can I directly send it to you? According to them, it is confidential.

Regards,

Maynard

Hi Team,

Good day, I have sent email last Feb 12. 

If there other information you want from the customer, please let me know.

Thank you.

Regards,

Maynard

Hi Maynard,

The schematic looks fine. 

Here are my feedback to the register settings.

{0x2F, 0x6000}, --> 0x0000 (please try with no dithering)

{0x23, 0x1805}, --> 0x1807 (RFoutTX type should be push-pull)

{0x06, 0x8D63}, --> 0x8C65 (CHDIV1 x CHDIV2 cannot be equal to 40, otherwise we cannot get 16x MHz output. MULT cannot be equal to 3 with PLL_R_PRE = 1.)
{0x05, 0x0101}, --> 0x0102 (change PLL_R_PRE = 2 in order to meet the input frequency requirement of MULT)
{0x03, 0x1200}, --> 0xA600 (I suggest set PLL_DEN = 960000 in order to make phase noise better)

Channel A frequency

{0x04, 0x3015}, --> 0x301A (I have reduced the fpd frequency, so PLL_N becomes 26)
{0x03, 0xA600}, --> moved this register to the Common synth registers, PLL_DEN is usually fixed for all necessary output frequencies.
{0x02, 0xC6C0}, --> 0x9660 (for channel A frequency)
{0x01, 0x7A2D}, --> 0x0E0E (for channel A frequency)

Channel B frequency

{0x04, 0x3017}, --> 0x301B (I have reduced the fpd frequency, so PLL_N becomes 27)
{0x03, 0xA600}, --> moved this register to the Common synth registers, PLL_DEN is usually fixed for all necessary output frequencies.
{0x02, 0x2559}, --> 0x0FA0 (for channel B frequency)
{0x01, 0x7A06}, --> 0x0E00 (for channel B frequency)

Hi Noel, 

Thank you for your response.

I have sent you an email regarding the response of the customer, were you able to receive it. I was instructed that I cannot post it  here in forum.

Looking forward for your kind response.

Regards,

Maynard