We are developing Zynq RFSoC based board for 64CH ADC sampling. For the same, we are using 4 RFSoC boards each with LMK04828 CLK synthesizer.
The CLKIN for all the LMKs is from single oscillator source.
Since we need to sample all ADC channels with as less as possible phase delay, so could you let us know how to SYNC multiple LMK04828
Hi Timothy,
One simple question. If LMK guarantees very less phase delay between input and output clock [In ZDM Dual Loop]
So why cannot we use individual 4 LMK's on each board and supply them with single source OCXO clock [with power divider] and expect all the clock output of each LMK to be in phase with input.
Hi Timothy,
If my above scheme would give me all LMK outputs in phase with input reference clock, then why do we need to have Master LMK and Slave LMK concept
as suggested
I do not want to use CLKin0 pin.
For the above suggested points, could you please provide brief block diagram ?
Hello Shekhar,
The Master LMK and Slave LMK is not required. You can carry forward by supplying the 4 LMK boards with a single source OCXO clock.
When Timothy is discussing SYSREF alignment, he is stating the you have to feed the SDCLKoutx back as a reference. The SYSREF is feed back into the FB Mux shown in the red box in the image below.
Since you do not want to use CLKin0, the second method Timothy discussed will not work for you.
Regards,
Kia Rahbar
Hello Shekhar,
ZDM dual PLL loop with SYSREF divider feedback is a possible configuration for synchronization.
DCLKout and SDCLKout can be in phase if the steps described in the Synchronization of Multiple LMK0482x Devices application note are followed.
Please note there are three synchronization methods for synchronizing multiple LMK04828 devices. These methods along with their pros and cons are shown below:
A further description of each of these synchronization methods can be found here: https://www.ti.com/lit/an/snaa294/snaa294.pdf
Regards,
Kia Rahbar
Hi Kia,
I am clear that if we give Single source reference clock to all LMKs, DCLK of each will be in-phase. But will SDCLKs of each LMK be in-phase ? Because SDCLK is ouput of sysref divider and
As per Derek Payne " there could be variations in the power-up or register programming for each card, you do not know what the LMK04828 R-divider phase will be. LMK04828 also does not have a way to reset the R-divider phase, so even if you put the SYSREF in the feedback loop and tried to synchronize all the SYSREF dividers you would still be unable to ensure the correct final phase is achieved"
Here I want all my "Analog SYSREF" to be in-phase and also all "PL SYSREF" to be in-phase
Will this work ?
Hello Shekhar,
When using a single reference clock, the SDCLKs of each LMK will be in phase if a low input frequency is used (see highlighted text below).
Regards,
Kia Rahbar
