LMX2820: Confirmation regarding SYSREF divider

Hi Jonathan,

I'm not sure what is meant by an "open" N-divider... since the channel dividers operate on powers of two, and the VCO range extends from 5.5GHz to 11GHz, normally a continuous frequency range is achieved by changing the VCO frequency and the corresponding N-divider value.

1. SYSREF_DIV_PRE cannot be bypassed, and must be active to establish a divide value within the nominal interpolator frequency range of 800MHz to 1600MHz.

2. 4 to 4096

3. Only even divides are permitted.

4. The interpolator and the SYSREF delay circuit introduce slightly higher noise overall compared to a standard RF output. Phase noise on the SYSREF output has not been evaluated very closely, because normally as long as the edge jitter is significantly smaller than the delay adjustment step size the overall noise of the SYSREF output is not important to its proper function.

Regards,

Hi Jonathan,

I still don't understand the contention by the customer that the channel divide ratio cannot support certain frequencies. True, they cannot support 350MHz from 5950MHz VCO. But they can from 5600MHz VCO with divide-by-16. The whole point of supporting an octave range on the VCO is that it allows complete frequency coverage with power-of-2 dividers. So 5500-11000 is covered by direct VCO output, 2750-5500 is covered by divide-by-2, 1375-2750 is covered by divide-by-4, etc. They can modify the N-divider value to select the appropriate VCO frequency to synthesize any required output frequency.

Does the customer require a fixed VCO frequency? The use case for this device has been optimized around changing the VCO frequency for synthesizing any frequency down to about 50MHz.

It sounds like what the customer wants is a fractional output divider. While it would be nice to have an output divider that can synthesize any frequency from an integer PLL, in practice TI makes PLLs with sigma-delta fractional dividers since this is a well-understood architecture, there is digital circuitry composing the fractional component of the divider that must be operating around an order of magnitude higher frequency than the output divide, and consequently the maximum input frequency to the sigma-delta fractional dividers used in our synthesizers is limited to less than 1GHz (internally, the integer portion of the N-divider pre-scales the frequency considerably). The sigma-delta fractional divider approach is great when the output frequency range for the divider is not too high (for example, when the range is equal to the phase detector frequency range) and when the input source is high enough frequency that the digital circuitry can be clocked at high speed relative to the output frequency; but it would not be possible for the sigma-delta fractional divider to take 5500MHz in and give 5495MHz, 2800MHz, or 1.213141GHz out, because all of those frequencies are above the usable maximum output frequency range of the divider. You'll find that the "sigma-delta fractional N-divider + octave tuning range VCO with power-of-2 dividers" approach is standard across the industry, because generating arbitrary fractional divides at high frequency is (as of today) constrained to a range that is better suited for phase detectors than for direct output divides.

Additionally, we've investigated whether it makes sense to provide the fractional divider as an external component, but when faced with the limitations (<1GHz output frequency, sometimes drastically less, requires an order of magnitude higher frequency clock to drive the digital, added power requirements due to external I/O) most customers would rather just use the PLL synthesizer.

Regards,

Hello L,

Thanks for the clarification, I now understand what you're getting at regarding opening the N-divider. I think the biggest limitation is that it adds another mux in the feedback path, which impacts the PLL noise performance and the device current; we'd also need to route the N-divider output to some pins, which means either another mux or sacrificing a feature somewhere else. But now that I understand the request and the reasoning behind it, I will keep it in mind for planning future devices.

The 1/f noise is normalized to 1GHz, but the noise value in the datasheet is given for the 10kHz offset - in other words, we give PN_flicker_10kHz. So to compute the phase noise at 10kHz offset for a 6GHz output carrier, and with the current typical value of -134dBc/Hz, we have:

PN_flicker = PN_flicker_10kHz - 10log(offset/10kHz) + 20log(Fout/1GHz) = -134dBc/Hz - 0 + 15.56dBc/Hz = -118.44dBc/Hz

The calculation above matches your result in your first example (slightly different given flicker noise, but otherwise equivalent calculation). Your other method is essentially the same as the first method, but with an additional scaling to 100MHz that changes the result; the extra scaling to 100MHz is not valid.

Regards,

L,

The 1/f noise is independent of input frequency and PFD frequency. Whether you have a 100MHz, 500MHz, or 10kHz reference, the 1/f noise remains the same. This can be seen with a simple experiment: using PLLatinum Sim (PLLATINUMSIM-SW), load the LMX2820 profile, ensure that there is no multiplier being used in the reference path, and apply any valid combination of input reference and PFD frequency. You will find that the 1/f component of the noise does not change. (The multiplier adds around 1.5dB to the 1/f noise across all frequencies.)

1/f noise is normalized to 1GHz (and typically given at the 10kHz offset) by convention. We could pick any frequency to set the 1/f noise, but practically we choose the industry convention because it makes it very straightforward to compare device performance both between TI PLLs and between competitor PLLs.

The 1/f noise only scales with output frequency. You can scale the 1/f noise to any arbitrary output frequency by adding 20log(Fout/1GHz). 

Since each octave of 1/f noise carries an equal noise energy, it follows from the math that the 1/f noise has a slope of about -3dB/octave or -10dB/decade. Consequently, to compute the 1/f noise for any given offset, in addition to scaling the 1/f noise to the desired frequency, the increase or decrease due to the difference in offset must be included as well, hence the factor of 10log(Offset/10kHz).

I mentioned it above but I'll focus on it here: TI provides a tool, PLLatinum Sim (PLLATINUMSIM-SW) which can be used to determine the phase noise characteristics for many of our PLLs (including the LMX2820). If you are not already using it, I strongly recommend using PLLatinum Sim to simulate device performance.

Regards,