150 mhz 32 bit counter

I do not need to generate a clock but I need a 32 bit counter with 32 parallel outputs that will receive a RF signal of up to 150 MHz as input (properly amplified of course) for 1 second of time and then tell me the exact frequency down to the single hertz. 

Hello Alvin,

Sorry for the confusion. We have another Responsible Organization that will discuss with you the options here at TI.

I'll transfer this over to them now!

Alvin,

While we await a response from the other team, I want to point out that this seems like something you could handle with a CPLD and an RF-to-CMOS buffer. To be more precise, it sounds like you need some basic building blocks:

• A precise reference such as an OCXO or some kind of GPS lock, which has an accurate representation of one second
• A counter that can count up to 150MHz, and another counter for your precise reference
• A mechanism to synchronously enable or disable the measurement counter from the reference counter
• Some device which can accept an RF signal in, and produce a counter-compatible signal out (LVCMOS or equivalent)

I think the easiest option for a high precision reference is an LVCMOS OCXO (there are many at 10MHz which works well with most discrete or CPLD digital logic). If you have some other reference in mind, we could offer more guidance about how best to use it (if needed).

The counter is the simplest of these building blocks; a good starting point is the cascaded SN74LV4040A, operational up to around 75MHz with light loading at 3.3V supply (higher at 5V, but doesn't function with 3.3V I/O then), which should be sufficient for any OCXO or frequency reference, and gets most of the way to a good measurement counter. I checked our counter portfolio but I don't think we have any discrete counters rated for 150MHz at 3.3V; consequently, the first stage (or two, to be safe) into the measurement counter should probably be driven by D-flip-flop(s) with Qbar tied to D (e.g. SN74AUP2G80). Again, a single CPLD could likely replace all of these counters, though you may still want to add a stage or two of external D-flip-flops to reduce the input frequency range to the CPLD if there are any worries about meeting setup and hold requirements at 150MHz. Note that preset and clear are not necessary for operation: you can always just perform the difference between the start and the stop counts.

You will also need some logic to reset the counter and decode the reference count to a start-stop enable pulse lasting one second. A discrete implementation might involve a handful of digital comparators (e.g. SN74HC688) looking for the exact value of one second of reference pulses, triggering an S-R latch tied to the counter clear and the measurement counter window; some measurement toggle could reset the latch to begin the measurement count, the reference counter would exit the clear condition and begin counting, and would automatically halt at the preprogrammed value. Again, this could be done with a CPLD as well, for much lower cost and component count.  

To convert your measurement RF signal to an LVCMOS signal, an input buffer like LMK00804B could be used. Since LMK00804B has a synchronous enable, starting and stopping the frequency counter cleanly is very easy: attach the enable to your reference counter S-R latch or your CPLD equivalent. If your measurement signal is always going to be around 150MHz there likely will not be problems with slew rate, but if the measurement signal could be lower frequency (e.g. 15MHz) this could cause issues with slew rate; an alternate low-frequency path through a high-speed comparator may be advisable.

Regards,

All I asked for is the counter. I can do all the glue logic as well as do most of it with a microchip pic computer. I do not need precise timing for the 1 second interval. a 32768 crystal is good enough for my receiver output. What d flipflop is rated for 5 ns? What was the 75 MHz 32 bit counter?

I need 5 volt devices