LMX2820EVM: LMX2820EVM using PFD input and external mixer

Hi Jonathan,
                     My understanding of this is that the VCO calibration scheme might be taking information from the N counter and that's why when you use the internal PFD with the mixer approach the "frequency" information is lost and therefore the VCO calibration might cause a runaway effect losing lock. My suggestion is to wait for the loop to lock without using any VCO calibration which unfortunately will take some time.

Note in the internal PFD with the mixer approach, the phase of the output of the mixer will depend on the phase of the LO signal and thus the PLL loop will need to recalibrate to acquire phase lock. 

I will check with my chip design team to understand what exactly the VCO calibration scheme incorporates and if there is an impact on using it in the internal PFD approach. I expect this to take a few days.

Thanks,

Great,thanks Badarish.  I will try that.  I assumed the 'calibrate VCO' also programmed the registers.

Best regards

Jon

Hi,

I've experimented with the evaluation board a bit more, initially programming the board using the internal feedback path.

I then switch the PFD_SEL path for the input to be from the PFD_IN pin, bypassing the internal N counter.  If I switch off my LO this doesn't affect the output frequency.  I would expect the synth to lose lock if I did that.  Also if I change the N counter setting, even though according to the GUI graphic that path is bypassed, the output frequency changes.  So its as though the LMX2820 has not been programmed correctly to use the external PFD input pin.

Best regards

Jon

Jon,

For the mixing down approach, what you do is:

1. Do NOT use instant calibration or dubble buffering (shadow registers)

a. I'm not sure if instant calibration works with external mixer or not, but let's not bring in more complication into this

b. For double buffering, it ignores the register write until the R0 register is written.  On TICSPro, go to "User Controls" under "General Controls", ensure all the 4 double buffering bits are disabled

2.  Lock the PLL normally without using the mixer or LO and calibrate the VCO

3. Power up your LO and switch over to internal mixer mode with the PFD_SEL bit.  NOte also that the PFD_SINGLE bit also automatically changes.

Regards,
Dean

Hi Dean

Thanks for your reply, I've already tried this.  When I disable the LO in the feedback loop, the synth remains locked.  I would expect it to drop out of lock if its was using the PFD feedback path as there'd no longer be a feedback signal.

I'm not convinced the feedback path is being selected internally (even though I'm configuring the register).  I've checked the internal registers and even manually written to them, so they appear to be being programmed correctly.

Jon

Hi Dean

Thanks for your reply.  I was already doing this but thought I'd better check the registers directly, ensure they are being programmed.  They are.  And I've tried writing directly to the raw registers but this made no difference.

In the setup you describe above, I do this and when I've switched over to external mixer mode and disable the LO to the mixer, the synth still remains in lock (which it shouldn't given the feedback signal is no longer present).

Thanks

Jon

Hi Jonathan,

I checked with the design, set R57[0] and R15[10:9] is good enough to put the part to accept PFDIN. 

Currently I don't have lab access, so would like to ask your help to do some debug.

1. set R1[5] = 1 and R17[6] = 1. This will make sure the lock detector will continuously monitor the Vtune voltage in order to reflect the true lock status.

2. program the part to lock to a certain frequency

3. program R57[0] = 0 to enable PFDIN. I would expect it will lose lock because there is no PFDIN signal. 

If it does not lose lock, increment PLL_NUM by 1 (e.g. from 0 to 1), will the output frequency follows the change?

Hi Noel,

Thanks for the suggestions.  Upon initialisation of the Eval board R1[5] and R17[16] are already set to 1.

I followed what you suggested, programming the LMX2820 to lock to a certain frequency.  I then programmed R57[0] to 0 to enable PFDIN however it did not lose lock.  Furthermore when I incremented the PLL_NUM by 1, the output frequency followed the change.  Visually the GUI shows the N divider (PLL_NUM) path bypassed, so it shouldn't have followed PLL_NUM.

I'm a bit stumped.  Doesn't appear to be working (i.e. disabling the internal feedback path forcing the internal VCO to lose lock)?

Thanks

Jon

Hi Jonathan,

I am asking my colleague to verify this, please stay tuned, I will get back to you later.

Hi Noel,

Thanks for that - I don't suppose there's any update is there?

Thanks

Jon