Hello Sai,
It isn't possible to reliably generate 32.665MHz SYSREF frequency through the dividers on the LMX2820 when the VCO is set to 8884.2MHz. Refer to the diagram below:
In order to get 32.665MHz from 8884.2MHz, you must divide by 272. Additionally, the SYSREF_DIV_PRE output frequency (the interpolator frequency) must be between 800MHz and 1600MHz. This is only possible by setting SYSREF_DIV_PRE to divide-by-8. 272 / 8 = 34. Additionally there is a divide-by-2 block after the SYSREF_DIV, so the remaining SYSREF_DIV must be 17; this is not possible, since the SYSREF_DIV only includes even divides. If you try to use SYSREF_DIV_PRE with divide-by-4, the programmable delay steps will likely become nonlinear and will no longer work.
In practice, it is possible to get 32.665MHz by ignoring the limits on the interpolator frequency and setting the SYSREF_PRE_DIV to 4:
The output performance of the SYSREF clock will be degraded compared to the device clocks. Otherwise, the output format, common mode, and other behavioral characteristics are the same as the RF output buffers. Into high-impedance I measure around 2V common mode voltage, with a low of 1V and a high of 3V, at each pin. Expect the amplitude to be reduced by about half when driving a 50Ω load.
Regards,
Sai Kiran,
Compare the phase noise plot below, taken from the channel divider maximum divide at an arbitrary VCO frequency, vs. the SYSREF output phase noise data in the previous post. There is around 10dB worse performance at the SYSREF noise floor, and the RF output is 1.5x higher frequency.
I don't have any data on the SYSREF VODIFF min/max, because as far as I can tell this has not been characterized. Based on the previous post phase noise plot, it looks like just under 10dBm output power differential into 100Ω load (measured through a 2:1 impedance balun into 50Ω single-ended), which is just under 2Vpp VOD.
Regards,
