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CDCLVC1310: Pull up info

Dilip Namdeo Mohol
Intellectual 2100 points
Part Number: CDCLVC1310


Hi ,

One of my customer is using CDCLVC1310 .

They Doc1.docx are connecting LVCMOS (3.3V) to PRI_INP (pin#13).

PRI_INN is just connected with 1K pull up and pull down.

 

As per figure-3 in datasheet, they have mentioned 100 ohm pull-up and pull-down on input.

 

  1. What is the reason for this pull-up and pull down ?
  2. Can I change this to 1K as I am not able to meet the spec with 100 ohm pull-up and down.

 

 

  • 0
    TI__Genius 13870 points

    Hello Dilip,

    The reason for these resistors are for impedance matching. Ideally, a typical LVCMOS signal is terminated as below and has limited recommended termination lines of <1/4th the wavelength of the highest harmonic frequency.

    Other ways of impedance matching are shown below, although, these configurations require more power:

    R1 || R2 must be 50 ohms. Hopefully this helps.

  • 0 in reply to Aaron Black
    TI__Genius 13870 points

    Hello Dilip,

    The CDCLVC1310 itself was tested using the attached image previously.

    If 1k ohm resistors are used the reflections would be similar to if these were left open, thus removing the need of these resistors.

  • 0 in reply to Aaron Black
    Prodigy 10 points

    HI Aaron,

    Thanks for your response.

    with your response I understand that R1 and R2 are only for impedance matching.

    And if we are fine from reflection perspective we can have only series resistor without R1 and R2 (pull up and pull down), same as mentioned below ?

    Please confirm.

    Thanks

    Kapil

  • 0 in reply to Kapil Jain
    TI__Genius 13870 points

    Hello Kapil,

    That is correct, R1 and R2 are not required.

    Typical LVCMOS application as noted above does not have this connection at all.