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LMK04826: Issue configuring dynamic delay

Evan Shelley
Prodigy 20 points
Part Number: LMK04826
Other Parts Discussed in Thread: LMK04828-EP

Hello,

I have been trying to use the LMK04826 to generate two clock signals, and dynamically apply delay to one of these signals. I have been testing on DCLKout4 and DCLKout6, trying to run something similar to the example case shown on page 44 of the LMK0482x documentation, but with DCLKout6 as the static clock and dynamically changing the phase of DCLKout4. Both clocks are divided by 24, converting the VCO frequency of 1966MHz to 81.92MHz. In order to delay DCLKout4 by one VCO cycle, the documentation suggests setting DCLKout4_DDLY_CNTH = 12 and DCLKout4_DDLY_CNTL = 13, as on page 43, table 3 of the documentation. When taking measurements, I am able to verify that I can dynamically update the phase of DCLKout4, however it does not use the CNTH and CNTL values I set, but instead uses the POR default values of CNTH = 5 and CNTL = 5. 

I read some other forum posts here regarding issues with dynamic delay and some stated that CNTH and CNTL cannot be updated during runtime, but instead should be set initially and will only use those values. I have included my register write sequence below for programming the chip. Despite only changes the CNTH and CNTL registers during initial setup, they still do not seem to update. I have tried a number of things, such as asserting the POWERDOWN value in register 0x002 during all register writes then deasserting at the end, pulsing POWERDOWN at the end, holding RESET at address 0x000 during all register writes and deasserting at the end, writing CNTH and CNTL values for all clocks, testing on DCLKout0 and DCLKout2 as in the example, but none of these have had any affect. Any help with this problem would be appreciated.

Here is the register write sequence:

Setup:

TI Clock Chip Reg: 0x0: writing 0x90
TI Clock Chip Reg: 0x0: writing 0x0
TI Clock Chip Reg: 0x2: writing 0x0
TI Clock Chip Reg: 0x100: writing 0x18
TI Clock Chip Reg: 0x101: writing 0xCD
TI Clock Chip Reg: 0x103: writing 0x0
TI Clock Chip Reg: 0x104: writing 0x2
TI Clock Chip Reg: 0x105: writing 0x0
TI Clock Chip Reg: 0x106: writing 0xF0
TI Clock Chip Reg: 0x107: writing 0x1
TI Clock Chip Reg: 0x108: writing 0x18
TI Clock Chip Reg: 0x109: writing 0xCD
TI Clock Chip Reg: 0x10B: writing 0x0
TI Clock Chip Reg: 0x10C: writing 0x2
TI Clock Chip Reg: 0x10D: writing 0x0
TI Clock Chip Reg: 0x10E: writing 0xF0
TI Clock Chip Reg: 0x10F: writing 0x1
TI Clock Chip Reg: 0x110: writing 0x18
TI Clock Chip Reg: 0x111: writing 0xCD
TI Clock Chip Reg: 0x113: writing 0x0
TI Clock Chip Reg: 0x114: writing 0x2
TI Clock Chip Reg: 0x115: writing 0x0
TI Clock Chip Reg: 0x116: writing 0xF0
TI Clock Chip Reg: 0x117: writing 0x1
TI Clock Chip Reg: 0x118: writing 0x18
TI Clock Chip Reg: 0x119: writing 0xCD
TI Clock Chip Reg: 0x11B: writing 0x0
TI Clock Chip Reg: 0x11C: writing 0x22
TI Clock Chip Reg: 0x11D: writing 0x1D
TI Clock Chip Reg: 0x11E: writing 0xF1
TI Clock Chip Reg: 0x11F: writing 0x1
TI Clock Chip Reg: 0x120: writing 0xC
TI Clock Chip Reg: 0x121: writing 0xCD
TI Clock Chip Reg: 0x123: writing 0x0
TI Clock Chip Reg: 0x124: writing 0x2
TI Clock Chip Reg: 0x125: writing 0x0
TI Clock Chip Reg: 0x126: writing 0xF9
TI Clock Chip Reg: 0x127: writing 0x0
TI Clock Chip Reg: 0x128: writing 0x18
TI Clock Chip Reg: 0x129: writing 0xCD
TI Clock Chip Reg: 0x12B: writing 0x0
TI Clock Chip Reg: 0x12C: writing 0x2
TI Clock Chip Reg: 0x12D: writing 0x0
TI Clock Chip Reg: 0x12E: writing 0xF1
TI Clock Chip Reg: 0x12F: writing 0x0
TI Clock Chip Reg: 0x130: writing 0x18
TI Clock Chip Reg: 0x131: writing 0xCD
TI Clock Chip Reg: 0x133: writing 0x0
TI Clock Chip Reg: 0x134: writing 0x2
TI Clock Chip Reg: 0x135: writing 0x0
TI Clock Chip Reg: 0x136: writing 0xF1
TI Clock Chip Reg: 0x137: writing 0x1
TI Clock Chip Reg: 0x138: writing 0x11
TI Clock Chip Reg: 0x139: writing 0x2
TI Clock Chip Reg: 0x13A: writing 0x0
TI Clock Chip Reg: 0x13B: writing 0x20
TI Clock Chip Reg: 0x13C: writing 0x0
TI Clock Chip Reg: 0x13D: writing 0x1
TI Clock Chip Reg: 0x13E: writing 0x0
TI Clock Chip Reg: 0x13F: writing 0x4
TI Clock Chip Reg: 0x140: writing 0xA
TI Clock Chip Reg: 0x141: writing 0x0
TI Clock Chip Reg: 0x142: writing 0x1
TI Clock Chip Reg: 0x143: writing 0x11
TI Clock Chip Reg: 0x144: writing 0xFF
TI Clock Chip Reg: 0x145: writing 0x7F
TI Clock Chip Reg: 0x146: writing 0x18
TI Clock Chip Reg: 0x147: writing 0x4A
TI Clock Chip Reg: 0x148: writing 0x2
TI Clock Chip Reg: 0x149: writing 0x2
TI Clock Chip Reg: 0x14A: writing 0x2
TI Clock Chip Reg: 0x14B: writing 0x16
TI Clock Chip Reg: 0x14C: writing 0x0
TI Clock Chip Reg: 0x14D: writing 0x0
TI Clock Chip Reg: 0x14E: writing 0xC0
TI Clock Chip Reg: 0x14F: writing 0x7F
TI Clock Chip Reg: 0x150: writing 0x3
TI Clock Chip Reg: 0x151: writing 0x2
TI Clock Chip Reg: 0x152: writing 0x0
TI Clock Chip Reg: 0x153: writing 0x0
TI Clock Chip Reg: 0x154: writing 0x78
TI Clock Chip Reg: 0x155: writing 0x0
TI Clock Chip Reg: 0x156: writing 0x78
TI Clock Chip Reg: 0x157: writing 0x0
TI Clock Chip Reg: 0x158: writing 0x96
TI Clock Chip Reg: 0x159: writing 0x0
TI Clock Chip Reg: 0x15A: writing 0x78
TI Clock Chip Reg: 0x15B: writing 0xD4
TI Clock Chip Reg: 0x15C: writing 0x20
TI Clock Chip Reg: 0x15D: writing 0x0
TI Clock Chip Reg: 0x15E: writing 0x0
TI Clock Chip Reg: 0x15F: writing 0xB
TI Clock Chip Reg: 0x160: writing 0x0
TI Clock Chip Reg: 0x161: writing 0x2
TI Clock Chip Reg: 0x162: writing 0x5
TI Clock Chip Reg: 0x163: writing 0x0
TI Clock Chip Reg: 0x164: writing 0x0
TI Clock Chip Reg: 0x165: writing 0x2
TI Clock Chip Reg: 0x171: writing 0xAA
TI Clock Chip Reg: 0x172: writing 0x2
TI Clock Chip Reg: 0x174: writing 0x0
TI Clock Chip Reg: 0x17C: writing 0x18
TI Clock Chip Reg: 0x17D: writing 0x77
TI Clock Chip Reg: 0x166: writing 0x0
TI Clock Chip Reg: 0x167: writing 0x0
TI Clock Chip Reg: 0x168: writing 0x2
TI Clock Chip Reg: 0x169: writing 0x59
TI Clock Chip Reg: 0x16A: writing 0x20
TI Clock Chip Reg: 0x16B: writing 0x0
TI Clock Chip Reg: 0x16C: writing 0x0
TI Clock Chip Reg: 0x16D: writing 0x0
TI Clock Chip Reg: 0x16E: writing 0x3B
TI Clock Chip Reg: 0x173: writing 0x0
TI Clock Chip Reg: 0x1FFD: writing 0x0
TI Clock Chip Reg: 0x1FFE: writing 0x0
TI Clock Chip Reg: 0x1FFF: writing 0x53
TI Clock Chip Reg: 0x2: writing 0x1
TI Clock Chip Reg: 0x2: writing 0x0

Modified during runtime:

Turn off all clocks except clk4 and clk6
TI Clock Chip Reg: 0x106: writing 0xF8
TI Clock Chip Reg: 0x10E: writing 0xF8
TI Clock Chip Reg: 0x126: writing 0xF8
TI Clock Chip Reg: 0x12E: writing 0xF8
TI Clock Chip Reg: 0x136: writing 0xF8
Setup dynamic phase delay for clk4
TI Clock Chip Reg: 0x116: writing 0x70
TI Clock Chip Reg: 0x141: writing 0x4
TI Clock Chip Reg: 0x144: writing 0xFB
TI Clock Chip Reg: 0x143: writing 0x13
TI Clock Chip Reg: 0x143: writing 0x12
TI Clock Chip Reg: 0x139: writing 0x2

Shift phase:

TI Clock Chip Reg: 0x142: writing 0x1

  • 0
    TI__Mastermind 30220 points

    Hi Evan,

    The LMK04826 documentation needs an update, because there are several shadowed registers for the dynamic digital delay (e.g. DCLKout4_DDLYd_CNTH) which are actually responsible for the dynamic delay values selected. Please see section 9.3.3.2 of the LMK04828-EP datasheet for better documentation (same registers, different VCO range) as well as 9.7.2.3 documenting the "missing" registers from LMK04826. Apologies for the oversight, I've added this to our next round of datasheet corrections.

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 20 points

    Hi Derek,

    Thank you for your response. This was indeed the issue, and I am now able to choose the amount by which the phase of the clock is dynamically updated.

    I however am now experiencing another issue in the consistency of these phase delays. Continually writing a 1 to the DDLYd_STEP_CNT results in random behaviour. Around 1 in 5 times, at random, the clock skips by a large number, not the 1 VCO cycle it should skip by. I have observed it skipping by instead 4, 7, or 10 VCO cycles, and others. These do not always occur at the same part of the cycle relative to the fixed signal. Due to the random nature of this occurring, I suspect it may be a failure in my SPI interface I use to write to the registers. However during initialisation many registers are written sequentially and the setup never fails to produce the same results, which is not consistent with the error rate I am observing when writing to DDLYd_STEP_CNT.

    So my question is have you ever observed this behaviour with the dynamic phase delays? I was also wondering if there is another way I can trigger these dynamic delay updates without writing to the DDLYd_STEP_CNT register?

    Thanks

    Evan

  • 0 in reply to Evan Shelley
    TI__Mastermind 30220 points

    Hi Evan,

    Have you already synchronized the dividers with the DCLKoutX_DDLY_CNTH/CNTL values set the same as the DDLYd register equivalents, to properly load the digital delay values? I don't see this anywhere in your initialization procedure, and the synchronization procedure should be required to achieve deterministic output divider/SYSREF phase.

    Approximately how long are you waiting between writes to the DDLYd_STEP_CNT register? A note in the LMK04828-EP datasheet indicates that you typically must wait 70ns + 1 period of the slowest clock for which dynamic digital delay is active, which should be around 85ns (less than the time required to perform a SPI transaction); If the SYSREF divider is somehow involved, this might be a little longer (judging by your programmed divider values), but in theory it should take less time than one SPI transaction for the delay to take effect.

    Regards,