I got some questions about the DDLY:
1. Can the DDLY be used together with the ADLY? If so, how should I set the DCLKoutn_max?
2. In manual 9.3.3.3, steps 6 and 7, both started with the SYNC_MODE, are they going to override each other?
Thanks
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I got some questions about the DDLY:
1. Can the DDLY be used together with the ADLY? If so, how should I set the DCLKoutn_max?
2. In manual 9.3.3.3, steps 6 and 7, both started with the SYNC_MODE, are they going to override each other?
Thanks
Hello Gang Huang,
1. Yes, DDLY can be used simultaneously with ADLY. Mux should be set to 0x3 (Analog Delay + Divider). If the divide value is odd, or if you also want to use the half-step, you should also enable half step and duty cycle correction for the analog delay path (DCLKoutX_ADLY_MUX=1).
2. Looks like a typo; step seven should not write a new value to SYNC_MODE. I'll add it to our list of datasheet corrections.
Regards,