This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK03200 output issues

Hello ti expert

      1:The current LMK03200CLK0-CLK7 can achieve the desired output frequency, please ask each output frequency, for example, CLK0_P(clk0) and CLK0_N(clk0*) frequency waveform is the same, if different how to configure?

      2:LMK03200LVPECL clock output frequency waveform is poor, how to configure how to solve?

     3:LMK03200LVDS clock output frequency waveform is better how to optimize, how to configure how to solve?

  • Hello,

    The clock output is differential, so the P and N port will be 180 degrees out of phase. The phase alignment can be achieved across all the outputs through SYNC functionality. Check load termination and impedance matching for waveform/signal integrity optimization.

    Regards,
    Hao