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LMK04828: PLL2_N_CAL questions

Kazuki Itoh
Genius 10710 points
Part Number: LMK04828
Other Parts Discussed in Thread: LMK04803

Hello team,

Could you please help me to address the customer's question?

  1. If PLL2_N is different from PLL2_N_CAL value (e.g. PLL2_N=0x10 and PLL2_N_CAL=0x0C), can guaranteed |ΔTCL| shift from the initial value?
  2. After the calibration, PLL2 uses the PLL2_N value. How can I check if the calibration is successfully completed? How long does it take to calibrate?
  3. In my system, sometimes the output port is not correct when start-up in low temperature (once in 20 start up. 1 unit in 100 prototype builds). 
    In this case, SPI, reset, power supply, and OSCin waveforms looks OK.
    However, when start up fails, it outputs high frequency. So I think it's related to the calibration.
    DCLKout7, 8, 10 ports are supposed to output 122.8MHz, but it outputs around 307MHz, which is close to default value. Register setting is same as mentioned in #2. Could you please help me to address this?
  4. 30.72MHz signal is input to OSCin. LMK04828 DS doesn't have formula about the relationship among PLL2_N, PLL2_N_CAL, prescaler, and VCO frequency. Would it be same as Table 116 and 117 in LMK04803 DS?
    In the 9.7.8.3, it indicates that PLL2_N_CAL prescaler is included. So I'd like to ensure that.
    Normal mode: PLL PDF (N) = VCO Frequency / (PLL2_P * PLL2_N)
    During calibration: PLL2 PDF (N_CAL) = VCO Frequency / (PLL2_P * PLL2_N_CAL)   

Best regards,

Itoh

  • 0
    TI__Guru** 107030 points

    Hi Itoh-san,

    Which operation mode (e.g. single PLL mode, buffer mode, etc) did you put it in?

    Could you give us more information like input frequency, vcxo frequency and vco frequency, etc?

    |ΔTCL| has no relationship to PLL2_N or PLL2_N_CAL, this parameter is related to the VCO only. 

    VCO calibration time should be very short as there is only one VCO core, I guess it is around maybe 10µs with 40MHz OSCin. 

    I don't aware that there is a mechanism to monitor the calibration status, I will have to ask somebody in the team who know this device better than me.

  • 0 in reply to Noel Fung
    TI__Genius 10710 points

    Hello Noel-san,

    The operation mode is Single-loop mode.

    VCXO=30.72MHz (=OSCin input frequency)
    VCO=2457.6MHz

    Configuration is same as Figure 27.

    Could you please answer question #3 and #4?

    Please find the internal link here for register setting. (Please connect to VPN for download)

    Regards,

    Itoh

  • 0 in reply to Kazuki Itoh
    TI__Guru** 107030 points

    Hi Itoh-san,

    Since PLL2_NCLK_MUX = 0, PLL2_N_CAL is not used. Furthermore, I don't think it is a VCO calibration issue due to PLL2_N_CAL. The VCO frequency is up to 2.6GHz only, if the output change from 122.88MHz to 307MHz is due to VCO frequency change, then the VCO frequency will have to be 6.5GHz. 

    In fact, it looks to me that the programming was not success, device was in the POR state. In this state, the clock divider is 8, with VCO0 being default at POR, the output clock frequency is therefore 307MHz. 

    Since in POR state, the output format, SDCLKouty_FMT, is "powerdown", you should not seeing valid signal, would you please confirm this?

  • 0 in reply to Noel Fung
    TI__Genius 10710 points

    Hello Noel-san,

    I mean 307MHz is confirmed at DCLKout8 (not SDCLKoutX).

    You mentioned PLL2_N_CAL is not used, but I don't understand this point well.

    The DS mentions the frequency calibration routine starts when 0x168 is programmed.

    So I thought PLL2_N should be same as PLL2_N_CAL.

    Do you mean the calibration routine will never run when PLL2_NCLK_MUX = 0?

    Regards,

    Itoh

  • +1 in reply to Kazuki Itoh
    TI__Guru** 107030 points

    Hi Itoh-san,

    Since customer's register is not disclosed here, let's take this offline.

  • 0 in reply to Noel Fung
    TI__Genius 10710 points

    OK, let's continue to resolve this offline