This chip has no clock output on our prototype and cannot be locked. Please ask us where to find out the problem.
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Hello HY,
Please provide more information about what input is being provided, what outputs were checked and what application this is meant to be used.
Please double check programming of register maps to make sure dividers are set properly and Fvco Frequency is within 2.39-2.55GHz (V1) or 2.94-3.13GHz (V2). The loop filter on the PLL also might not be set correctly, try other settings with Register 0.