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LMK04208: Enabling External Reference Clock Input to Clkin1 (J109) port of ZCU111

Shantharam Kalipatnapu
Prodigy 10 points
Part Number: LMK04208

Hi

 

We tried configuring Clkin1 port (J109) as input for providing a reference clock of frequency 10MHz from external reference to the ZCU111 board. For this we have disabled En_Clkin0 and enabled En_CLKin1 in Dual PLL Mode, Int VCO (of LMK04208 in TICS Pro v1.7.2.0) and selected Clkin1 to propagate to PLL1 input through the select MUX. We exported the HEX Register values and configured the clocks through SCGUI. However much to our surprise, we notice Clkin0 continues to propagate with its default frequency of 122.88MHz. This limitation in Dual PLL, Int VCO Mode is preventing us to use PLL1 achieve higher frequencies than the reference clock needed for our design. We are also attaching the Hex Register text files for the below shown two modes.

However in External VCO Mode, We could observe the reference Clock propagate to the ClkOut5 port (J108) through clock distribution network. Hence we could achieve only those frequencies less than or equal to the reference clock (10MHz) for operating the board.

 

We appreciate if somebody can help us in resolving this issue and help in enabling Clkin1 for referencing the external.

  • 0
    TI__Mastermind 18070 points

    Hello,

    We will get back to you next Monday.

    Regards,

    Hao

  • 0
    TI__Mastermind 31560 points

    Hello,

    Apologies for the trouble, it appears your attachment did not get uploaded. Could you please try uploading again?

    Based on the picture you provided, it doesn't seem that register settings would be responsible for the mix-up in CLKin0/CLKin1. To help rule out a register configuration issue, can you try setting R15[21] = 1? This bit is an override for the clock selection state machine, and should force the selected clock to the value specified by CLKin_Select_MODE independent of any state that could potentially be stuck in the clock selection state machine.

    Is it possible that the slew rate on the 10MHz signal source is not high enough, or that crosstalk from CLKin0 is somehow contaminating the CLKin1 input?

    Regards,

    Derek Payne

  • 0 in reply to Derek Payne
    Prodigy 10 points

    Hi Derek 

     

    Thanks for the reply. The files are attached now (Default Mode is DefaultMode.txt and ExternalRef.txt). - Files of LMK04208 

     

    We also tried setting R15[21]=1. This also doesn't seem to propagate Clkin1 external reference. Clkin0 seems to be the default clock taken despite using the config for the external clock reference (ExternalRef_R15.txt). 

    We measured the slew rate of the external 10MHz reference being provided. It is very similar to the 10MHz clock generated by internal PLL of LMK04208 and is less than 4% of the clock period (about 4ns).

    We are not sure about the crosstalk on the board but we don't think this can completely cut off the Clkin1 input.

    Any help in enabling the external reference clock in Dual PLL, Int VCO mode is appreciated.

  • 0 in reply to Shantharam Kalipatnapu
    TI__Mastermind 31560 points

    Hi Shantharam,

    Please note that TI security policy actually prevents me from accessing Google Drive through work PCs. In the future I recommend adding attachments through the E2E post "insert -> image/video/file" menu. For now I have loaded the configurations on a PC outside of work.

    Both files I received from you have the PLL1 R/N divider set equally, which does not match the image you originally provided. Upon diffing both files, I find that they are nearly identical, except ExternalRef has CLKin0_EN=0 and OSCin_FREQ=0.Please double-check that your ExternalRef configuration is actually configured how you desire, as the current configuration does not make sense with 10MHz CLKin1 reference and a 122.88MHz VCXO on the ZCU111 board.

    Regards,

    Derek Payne