LMX2571: RF frequency synchronizer solution

Hi team,

Please refer the feedback from customer about LMX2571. May I have help to verify about this two question?  Is there any other suitable part for their application?

• According to datasheet, The fout ‘s PN is not good for our application. For design request is to have the VCXO 122.88MHz supply good PN to IF mixer.                           Cannot LMX2571 support precise 122.88MHz frequency?
• And synthesizer ‘s function is used to implement 122.88MHz local oscillator. I think the LMX2571 integrate VCO function, it will degrade PN performance.

Not very familiar with RF synchronizer. Could you kindly help to provide your comment? Thanks.

Hi Feng bin,

When a PLL is working with a VCXO, the loop bandwidth will be very small so that the output phase noise is equal to the VCXO phase noise. As such, the phase noise of the PLL is not important as the loop filter will suppress PLL phase noise. 

We don't have single PLL anymore, I recommend LMX2430, which is a dual PLL. The IF PLL of LMX2430 can support 122.88MHz.

Hi Fung,

Thank for your feedback. 

My customer has simulate ADF4002 and  it cannot acheive customer's requirement as below figure.

May I have your help whether our LMX2430 can support it? Thanks.

Hi Feng bin,

What is the target loop bandwidth? The table said 2.5kHz while Figure 7 is showing a plot with loop bandwidth greater than 50kHz.

Hi Fung,

Figure 7 is located at ADI's datasheet.

I have discussed it with customer and it is for 5G application. So, the phase noise request is very high.

Originally, the mixer is using 122.88Mhz which is generated by VCXO directly and the phase noise request is as above table.

In this case, customer would like to build a system feature which need to sync the 122.88MHz of TX and RX. So, they need a additional RF synchronizer but the challenge will be the phase noise performance of it.

• Would you have the more suitable solution or suggestion for their requirement?
• If customer would like to do the total phase noise simulation, do we have this kind of tool? May I know which one can do it?

Hi Feng bin,

You confused me, what do they want to do? If they want to take a 40MHz input and lock to a 122.88MHz VCXO, then my suggestion is LMX2430 and the loop bandwidth is going to be narrow. 

Or they need a synthesizer that take 122.88MHz input and generate very high frequency with good phase noise? What is the output frequency and phase noise requirement?

Clock Design Tool has been faded out, please use PLLatinum Sim to do simulation.

Hi Fung,

Sorry to let you misunderstanding. I don't have this kind of experience before. It is the option one. 

They need to generate a 122.88Mhz with the spec of phase noise as below. If the loop bandwidth is low enough, the target phase noise spec is possible  to be achieved. Let me know if I am wrong. Thanks. 

Hi Feng bin,

Right, as long as the loop bandwidth is small enough, usually 10Hz to 20Hz, then the output phase noise will be almost equal to the VCXO phase noise. 

Hi Fung,

Thank for your help. I have tried to run the simulation result as below figure.

But, I am not sure why I cannot get the result with lower bandwidth.

Customer would also like to know whether there is any potential risks with low bandwidth setting.

My first thought will be that PLL needs more time to be locked. Do you have more comment about it? Thanks.