LMK05028: The VCO's phase timing with reference input

Amin-san,

Thank you for your feedback.
However, your answer seemed to be a little bit offset from our question.

We suspect that the DPLL in LMK05028 compares the phase difference between REF input and clock output from the on-chip VCO.

(Question) 
The fact we want to know is if DPLL check the phase difference between rising edge of the REF input and VCO clock,
or, falling edge of the REF input and VCO clock.
It is critical information for our application.

Kind regards,

Hirotaka Matsumoto

Hi Hirotaka -san,

How does that impact the application?

I will have to check with design and get back to you.

Regards,

Amin

Amin san

Thank you for your cooperation always.
The application is video camera with LMH1981+LMK05028.

LMH1981's Hsync signal connects to LMK05028 reference input.
When LMH1981's output contains jitter, LMK05028's lock releases sometimes.

Of course, we know that there is the DPLL lock threshold setting.
However, too enough threshold level, it cause lack of accuracy output frequency.
Therefore, we asked it.

Kind regards,

Hirotaka Matsumoto

Amin san

Thank you so much for your cooperation!
OK, we got it.

Kind regards,

Hirotaka Matsumoto