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LMK05028: PLL performance

Takumi Suzuki1
Mastermind 8630 points

Part Number: LMK05028

Hi,

Let me ask you a basic question about the performance of PLL as below.

My customer is considering to use this device for OTN/OUT system (10GbE <---> OTU2e, direct mapping from CBR10G3 to OPU2e).

The error margin of this system is +/-100ppm.

The question is that LMK05028 is available for this system, correct?

Following is the detail conditions of the customer's system.

 - XO : 25MHz +/-50ppm (max, including a change over the years)

 - TCXO : 20MHz +/-5.5ppm (max, including a change over the years)

 - IN_REF0 : 173.3707475MHz +/-100ppm (the synchronized output is 161.1328125MHz)

 - IN_REF1 : 161.1328125MHz +/-100ppm (the synchronized output is 173.3707475MHz)

 - PLL-MODE : 3-Loop Mode

Is it possible to use LMK05028 under the condition (+/-100ppm)?

And will you tell me the PLL-lock range under the condition?

In other words, is it possible to generate the output signal within +/-100ppm error against input signal error margin +/-100ppm?

The customer thinks it is no problem to use because there is an application note about "100GbE <--> OTU4" (SNAA314–April 201) on TI website.

Though the application note is about the example of +/- 20ppm system, the customer supposes no problem to use for +/-100ppm.

And lastly, will you tell me the "actual performance" of LMK05028, if possible? (error margin)

Thank you very much in advance.

Best Regards,

  • +1
    TI__Expert 6140 points

    Hello,

    I see you have listed out the requirements for all 3 loops inputs:

    1. APLL loop which locks to XO
    2. TCXO DPLL which locks to the TCXO
    3. REF DPLL which locks to the reference input

    When DPLLs are used, the output frequency is corrected to be 0 ppm vs the reference DPLL. So here's the breakdown:

    • 2 loop - APLL and TCXO DPLL  - output frequency error will match the TCXO error
    • 2 loop - APLL and REF DPLL - output frequency error will match the reference input frequency error
    • 3 loop - APLL, TCXO DPLL, REF DPLL - Output frequency error will match the reference input frequency error

    So if you're using 3 loop and reference is available and DPLL locked, the output frequency will match whatever the error is on the input frequency. Ref is off by 22 ppm, the output will be off by 22 ppm. The output will follow the reference until the point the reference is valid. There's many reference validation mechanisms but the key one here is ppm valid / invalid. You can set it tighter if need be, or you can set it at 100 ppm to make sure your reference remains valid throughout and the output follows it and stays locked to it.

    When reference is lost, device switches to holdover mode - trying to keep the output in the last known locked condition (DPLL uses history and averaging to derive this). However long-term stability in holdover mode is determined by XO in 2 loop mode, and TCXO in 3 loop mode.

    Lastly, device offers DCO feature - digital control oscillator. When device is locked, you can manually update the DPLL numerator (which feeds the APLL n divider and changes the VCO frequency, in effect changing the output frequency) through register writes. This feature allows for correction of output error on the ppb scale. So you can provide a 100 ppm error reference frequency and achieve tighter output stability by DCO through I2C.

    Hope that answers your questions.

    Thanks and regards,

    Amin

  • 0 in reply to Amin Eshraghi
    Mastermind 8630 points

    Hi Amin-san,

    Thank you very much for your kind reply !

    I understood and I will tell your answer to the customer.

    Thanks and Best Regards,