TPL5110: min time of DONE to DRV delay

Hello Ajayt,

Your first statement of the two is that there has to be a delay of 100ns minimum after DRV before DONE can transition from low to high as this pin is driven by a µC, this case would be a DRV-to-DONE relationship, tD_DONE has this reversed as it clearly indicates in Figure 1.

The statement '100ns is the minimum time that DRV takes to respond to the DONE input signal' relates to a DONE-to-DRV relationship and t_DONE states this as a minimum of 100ns.

Hopefully this helps!