Hi
For my new board design iam using the LMX2820 PLL for LO frequency generation, in the design i am providing 100MHz ref clock to the OSCIN input (single ended) ,My 100Mhz TCXO oscillator is 5V output level SO for translating the volatage level matching for LMX2820 iam using capacitive potential divider.same clock iam sharing to one more clock divider IC, for loading analysis of the same want the input capacitance of the LMX2820 OSCIN input pin.Kindly support me and also guide me to avoid the mistakes in the design scheme.
