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Original question:

LMK04828: Forwarding CLKin0 to SDCLKoutY

LMK04832: single pulse output

KGY
Intellectual 300 points
Part Number: LMK04832

Hi,

I was configuring 2 LMK04832 Eval board (master in ZDM,  slave in ZDM with reclocked clkin0) as discussed in the following thread

https://e2e.ti.com/support/clock-and-timing/f/clock-timing-forum/969294/lmk04828-forwarding-clkin0-to-sdclkouty?tisearch=e2e-sitesearch&keymatch=LMK04828%20reclock#

May i know if using the same master-slave configuration, can I send a pulse from the master LMK to all the slave LMKs so that all the slave LMKs will output a synchronized pulse?

Thanks.

  • 0
    TI__Mastermind 33790 points

    Hi KGY,

    That should still be possible with LMK04832, but there is some nuance to it because of the changes made to the LMK04832 SYSREF/CLKin0 circuits. The SYNC procedure outlined in the original post, along with the constraints of ZDM, ensures that the SYSREF dividers of the slave PLLs are all at the same phase. However, LMK04832 does not have a CLKin0 bypass path, and CLKin0 is incapable of triggering the pulser. In order to take advantage of the aligned SYSREF dividers, you can set the slaves for Re-Clocked SYSREF, so that the master pulse is re-clocked by the slave SYSREF divider at the same time across all devices. This also means that the pulse width will be twice as long at the slave, because the re-timer can only re-time at the rising edge of the SYSREF divider output. In theory this does not impact systems requiring JESD204B SYSREF, since the SYSREF edge timing with respect to the device clock is what matters, but it is good to be aware of this limitation when using CLKin0 SYSREF on LMK04832. And if this behavior is undesired, you could increase the master/slave SYSREF divider frequency to 12.5MHz, such that the slave device re-timing reduces the SYSREF frequency to the original 6.25MHz pulse at the output of each slave; since 12.5MHz is still the GCD for master and slave in both cases, all of the same synchronization procedures and guarantees still hold.

    You could also use the SYNC pin to trigger the pulser, as suggested in the original post. But that creates the additional challenge of triggering the pulse (with ~5ns setup time) on the same 6.25MHz (160ns) clock cycle across all devices, and I imagine any such method would require more signals and routing complexity from master to slaves.

    Regards,

    Derek Payne

  • 0
    Intellectual 300 points

    Hi Derek,

    I have already set slave LMK for reclocked SYSREF [SYSREF_MUX = Re-clocked].

    how to make master pulse to be re-clocked by the slave SYSREF divider?

    Thanks.

  • 0 in reply to KGY
    TI__Mastermind 33790 points

    KGY,

    When you trigger the master by toggling the SYNC pin or generating a pulser request through SPI, each slave device sees the SYSREF pulse on CLKin0, and re-times the pulse to its own in-phase SYSREF divider. The SYSREF mode outputs of the slave devices should repeat the pulse at 1/2 the frequency.

    If you are not seeing this, it's possible that your SYSREF phase is lagging your slave reference clock phase. The master's delays should be set so that the master SYSREF pulse edge occurs before the slave reference clock edge, to ensure that it is re-timed by the slave SYSREF divider (which should share an edge with the slave reference clock edge).

    Regards,

    Derek Payne

  • 0 in reply to KGY
    Intellectual 300 points

    Hi Derek,

    1.  I connected the outputs of one LMK (as master) to two LMK (as slave). i input 122.88MHz into clkin1 of the master LMK. I write into the registers of both slave LMK first, then the register of the master LMK. Then on the master LMK, i set the SYN_DISCx = '1'. I noticed that the phase relationship between the DCLKs of different slave LMKs are not fixed upon each power up. Is there anything that i set wrongly? I have attached the register files for the master and slave.

    2. to send the pulse to the slave LMK, after writing into the registers of master LMK and slave LMKs, i set SYSREF_MUX = pulser. then i send a single pulse from the master. i am not able to see the pulse at the outputs at slave LMKs. did i configure the LMKs wrongly?

    thanks.

    Fullscreen master.txt Download 
    R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D1
R5	0x000563
R6	0x000650
R12	0x000C51
R13	0x000D04
R256	0x010002
R257	0x01010A
R258	0x010280
R259	0x010340
R260	0x010410
R261	0x010500
R262	0x010601
R263	0x010755
R264	0x010818
R265	0x01090A
R266	0x010A00
R267	0x010B41
R268	0x010C20
R269	0x010D00
R270	0x010E01
R271	0x010F44
R272	0x011008
R273	0x01110A
R274	0x011280
R275	0x011340
R276	0x011410
R277	0x011500
R278	0x011601
R279	0x011700
R280	0x011818
R281	0x01190A
R282	0x011A90
R283	0x011B40
R284	0x011C10
R285	0x011D00
R286	0x011E01
R287	0x011F33
R288	0x012018
R289	0x01210A
R290	0x012200
R291	0x012341
R292	0x012420
R293	0x012500
R294	0x012601
R295	0x012711
R296	0x012808
R297	0x01290A
R298	0x012A80
R299	0x012B40
R300	0x012C10
R301	0x012D00
R302	0x012E01
R303	0x012F00
R304	0x013002
R305	0x01310A
R306	0x013280
R307	0x013340
R308	0x013410
R309	0x013500
R310	0x013601
R311	0x013733
R312	0x013820
R313	0x013903
R314	0x013A01
R315	0x013B68
R316	0x013C00
R317	0x013D08
R318	0x013E00
R319	0x013F0D
R320	0x014008
R321	0x014112
R322	0x014201
R323	0x014317
R324	0x014480
R325	0x014500
R326	0x014610
R327	0x01471A
R328	0x014802
R329	0x014942
R330	0x014A03
R331	0x014B06
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015001
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x01560F
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A01
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E1E
R351	0x015F0B
R352	0x016000
R353	0x016101
R354	0x01624C
R355	0x016300
R356	0x016400
R357	0x01650C
R361	0x016958
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017310
R375	0x017700
R386	0x018200
R387	0x018300
R358	0x016600
R359	0x016700
R360	0x01680C
R1365	0x055500
    Fullscreen slave.txt Download 
    R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D1
R5	0x000563
R6	0x000650
R12	0x000C51
R13	0x000D04
R256	0x010014
R257	0x01010A
R258	0x010200
R259	0x010341
R260	0x010420
R261	0x010500
R262	0x010601
R263	0x010744
R264	0x010814
R265	0x01090A
R266	0x010A80
R267	0x010B41
R268	0x010C20
R269	0x010D00
R270	0x010E01
R271	0x010F44
R272	0x011014
R273	0x01110A
R274	0x011280
R275	0x011340
R276	0x011430
R277	0x011500
R278	0x011601
R279	0x011714
R280	0x0118A0
R281	0x01190A
R282	0x011A80
R283	0x011B40
R284	0x011C10
R285	0x011D00
R286	0x011E01
R287	0x011F11
R288	0x012014
R289	0x01210A
R290	0x012280
R291	0x012340
R292	0x012420
R293	0x012500
R294	0x012601
R295	0x012710
R296	0x0128A0
R297	0x01290A
R298	0x012A80
R299	0x012B40
R300	0x012C10
R301	0x012D00
R302	0x012E01
R303	0x012F11
R304	0x013014
R305	0x01310A
R306	0x013280
R307	0x013340
R308	0x013410
R309	0x013500
R310	0x013601
R311	0x013714
R312	0x013800
R313	0x013901
R314	0x013A00
R315	0x013B14
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F0D
R320	0x01400B
R321	0x014103
R322	0x014200
R323	0x014314
R324	0x0144FF
R325	0x014500
R326	0x014618
R327	0x014718
R328	0x014802
R329	0x014942
R330	0x014A03
R331	0x014B06
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015001
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015604
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A04
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E1E
R351	0x015F0B
R352	0x016000
R353	0x016101
R354	0x01624C
R355	0x016300
R356	0x016400
R357	0x016509
R361	0x016958
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017310
R375	0x017700
R386	0x018200
R387	0x018300
R358	0x016600
R359	0x016700
R360	0x01680A
R1365	0x055500

  • 0 in reply to KGY
    TI__Mastermind 33790 points

    Hi KGY,

    A few comments:

    • Master device has SYSREF_MUX defaulted to continuous mode, I recommend re-clocked instead.
    • Both devices appear to have the DDLYdX_EN set. This is only required for dynamic digital delay, which changes the phase of the clock without synchronizing by adjusting the duty cycle over some number of clock cycles. DDLYdX_EN should be set to 0 for each output.
    • The slave LMK must have its SYNC_DISx bits set to 0 while the master SYSREF pulse into CLKin0 is being delivered, otherwise the output dividers will not be simultaneously synchronized.
    • Slave PLL2_N_CAL is set to 9, but should be set to 10 to match PLL2_N.

    Based on the master file, it looks like you should get SYSREF out of CLKout3 and CLKout9 when you switch the SYSREF_MUX to pulser mode and write to SYSREF_PULSE_CNT register. 

    Regards,

    Derek Payne