LMK05318: Setting up problems with configuration

Part Number: LMK05318
Other Parts Discussed in Thread: USB2ANY


I actually work with the network synchronizer LMK05318RGZT for generation of low-jitter reference clock of an FPGA-SERDES for optical communications.

So far I tried putting a configuration (tec_GG.TCS) from TICS Pro  onto the chip, but that doesnt work. In particular, reading/writing some registers on the LMK (from R101 onwards) gives errors and the device disappears from the I2C Bus and I need to repower the Board/Device to connect to it again using USB2ANY.

Is there maybe an error in my configuration ? The Schematics is almost eaqual to an evaluation Board (See SchematicREFCLK.pdf)

Thanks for help in advance

Roman E.


  • Hello Roman,

    Was the configuration generated from TICSpro tested on an EVM? I'm assuming no, just want to double check.

    Before doing any programming are you powering up in EEPROM mode? Does the device seem to be functioning best you can tell - best way to judge this is by the current consumption, is it 100s of mA. I see you have 24 MHz XO on your schematic so the factory EEPROM configuration will not lock since it's with a 48.0048 MHz XO.

    There's nothing different with regards to R101 and higher vs others.

    Also, just want to point out, the register address scheme is done in 2 bytes. Refer to section 9.5.2, figure 58, on page 58 (surprising figure and page number match) of the datasheet. The register address has includes register address high as well as register address low.

    I would recommend just doing one register write, for example power down and output channel, after boot up from EEPROM. This will help gauge whether your I2C transactions are working or not. You can get the exact command by using TICSpro and seeing it in the command dialog box. And yes even though the part will not be locked on your board (due to different XO) and there will be no output clock, you can still judge via the current consumption whether the update took or not. Power down and disabling a channel will have current savings.

    Thanks and regards,


  • Thanks for the fast reply,

    I´ll have a look soon and let you know whether that resolved already ;-)



  • Hello,-

    Thanks for the help so far, my voltages where quite low, after resolving that I dont have Register Problems or I2C-Problems anymore.

    In fact I got something to work somehow.

    With my configuration I could generate an output clock but only when Powering down the PLL 1 and power it up again. From startup even when the configuration is in the EEPROM, the device wouldn´t start, is that normal?

    Thanks in advance,


  • Hi Roman,

    That is not normal.

    So the factory EEPROM configuration will not result in an output clock. You have a 24 MHz XO on your board, is that correct? If so, the factory EEPROM configuration is for a 48.0048 MHz XO so it will not lock and have an output clock. You can connect an external sig gen into the XO_P pin at 48.0048 MHz just to see if factory configuration works or not.

    With regards to your configuration, did you follow the steps on TICSpro and then press runscript button?

    Thanks and regards,


  • Hello Amin,

    Yes I followed the instructions and pressed runscript. If The PLL already runs, runscript correctly also calculates the new frequency that I put in and generates it at the output, but from startup it wouldn´t work till I power down and up the PLL 1 once over the according registers.

    I´ll try to use a sig gen and the factory configuration today and try that out.

    Thanks and greetings


    Ps: And Yes, I use an 24 MHz XO

  • I have to correct a little

  • I have to correct a little

  • I have to correct a little,

  • I have to correct a little,

  • I have to correct a little,

  • I have to correct a little,

  • Oh,

    sth went crazy with my HMI.. ->

    I have to correct a little. It seems that the PLL 1 doesn´t lock. So the correct Frequency is generated just and only if I Powerdown the PLL1 and Reenable it again under APLL1 -> Powerdown (set first to "PLL1 Disabled" and then to "PLL1 Enabled" again).

    The Script runs through but with its soft reset clears any output and PLL1 wouldnt lock again. If I just change the Frequency and calculate again, the output immediately follows the new frequency.

    -> What could hinder the PLL 1 to lock?

    I tried just from interest to use PLL 1 cascaded after PLL 2 that would just generate an output after several enable/disable actions on PLL 1 and PLL 2.

    Sadly I dont have an Func-Gen that could produce more than 20 MHz here, I need to order another XO with 48.0048MHz to try out the factory setting.

    Greetings and regards


  • Hello Amin, 

    Thanks for helping! 

    I found the issue of that problem. The Filter in my schematic lowered the XO voltage so much, that the LOS_FDET_XO bit would always hinder the PLL1 to come up. Setting XO_FDET_BYP to 1 or removing that filter both resolved that issue and the LMK now even starts correctly and behaves accordingly.

    Thanks again and regards