CDCE6214: out0 and divider jitter

Stephen So

Prodigy 165 points

Part Number: CDCE6214

Do Out0 and other clocks derived directly from refclk have a jitter measurement?

Do the dividers preserve any jitter spec when the PLL is powered down and use refclk?

over 4 years ago

0 Hao Z over 4 years ago

TI__Mastermind 18070 points

Hello,

Yes there's max additive jitter of 350fs:

You can do RMS addition to calculate the final jitter. For example, if the input jitter is 500fs, then the total jitter is sqrt(500^2 + 350^2) = 610 fs.

Regards,
Hao

Clock & timing

Clock & timing forum

CDCE6214: out0 and divider jitter