Part Number: CDCE6214
Other Parts Discussed in Thread: 66AK2G12,
Hi
I look for compatible device or proper way to use this clock generator for feeding 100Mhz for Ti keystone 2 SOC 66AK2G12 and Xilinx Artix FPGA.
The SOC PCIE_CLK pins G2, F2 are defined as LVDS and their source power is 1.8V. Other electrical parameters are missing.
The SOC DDR_CLK is also defined as LVDS 1.8V with the following electrical parameters :
VIDH Input Differential High Voltage 100 mV
VIDL Input Differential Low Voltage -100 mV
The FPGA on the other hand, define the GTP transceivers to have:
ViDiff differential peak to peak input voltage min=350mV max=2000mV
Having this data I thought of using the CDCE6214RGET (because its high temperature105 T Amb.) with proper termination to feed the 3 clock inputs :
Please help me to confirm my design :
- Power VDDO_12 and VDDO34 with 1.8V
- Since the FPGA sewing is bigger than the 250mV LVDS, I thought of configuring the CDCE6214RGET to HSCL that getting VOH- VOL =660-150=510mv swing, which is ok with the FPGA requirement. I will use 100nF AC-Couple and put the HSTL output with no resistors attached to it. (no biasing pullup/down nor 100 Ohm) can you please say if that makes sense ?
- The other two SOC inputs I think of using LVDS outputs with AC-Coupled 100nF capacitors again without any termination or biasing resistors.
Please advise,
Avner
