LMK04828: Multi-board LMK Sync

Hi Timothy,

Thanks for the reply, I shall consider even-odd pairs for your device clocks & SYSREF.

we are following the below methodology for multi-LMK sync (2b), Ref Freq = Sysref Freq

Also Synchronization method as Zero Delay Mode, wherein ZDM rule is met, I do not need pulsed SYSREF to occur at the same time for both devices, using Dual loop mode with low Freq to PLL1

After the above considerations, will my scheme is fine?

NOTE: I do not want to use any Master/root LMK, neither I have a plan/scheme/option of using SYNC/CLKIN0 for sync purposes. 

Hi Timothy,

Modified Requirement

1] DCLK = 112.5MHz (Use internal RFSoC PLL to get 1350MHz)

2] SDCLK = 5.625MHz (Integer multiple of sampling CLK/16 i.e. 1350/16 = 84.375)

Now for this, we are using the below settings in TICS Pro

1. Input CLKIN0 is configured as 5.625MHz
2. The PLL1 phase detector is also configured as 5.625MHz
3. External VCO is chosen as 225MHz
4. The internal VCXO should be in the range of (2370 - 2630)MHz or (2920 - 3080MHz)MHz
5. The VCXO mux is configured as VCO0 as the frequency which has chosen is 2475MHz, 2475MHz is chosen because 2475/440 gives us 5.625MHz as the sys ref frequency
6. The feedback path is chosen as FB_MUX which eventually is SYSREF (Nested 0 Delay F/B)

1. SYSREF clock divider is chosen as 440 to get SYSREF Frequency as 5.625MHz
2. SYSREF_MUX is chosen as SYSREF continuous
3. SYSREF_CLKin0_mux is chosen as from SYSREF_MUX
4. From this configuration, we get the SYSREF_Frequency

1. DCLKs are used to generate high frequency, and SDCLK are used to generate low frequency
2. DCLK frequencies can be generated only through Internal VCXO Divider and SDCLK frequencies can be generated as SYSREF Frequency
3. As the SYS_REF we require is the same as the SYS_REF generated, it doesn't need to pass through any dividers, the clock output selection can be made SYSREF as shown. 
4. Clock divider value is chosen as 22 to get 112.5MHz

Please Validate the scheme and suggest changes if any...

Thanks 

Shekhar

Hi Timothy,

We are planning to carry out the expt in Xilinx RFSoC EVAL board (This has an LMK module)

Also, tell us to go ahead with LMK04828 orLMK04832.

And can we go ahead with the above set Phase Detector freq for both PLL1 and PLL2

Hi Timothy,

In one of the similar projects, we need our output clocks to be in phase with each other but not to be in phase w.r.t. input ref clock.

So can we ignore the first rule of ZDM i.e. I/P CLK = GCD (O/P CLK, I/P CLK), and only follow the 2nd rule i.e. lowest o/p freq as SYSREF feedback in ZDM nested topology?

With this, we shall get Deterministic phase w.r.t I/P. 

Hi Derek,

Thank you for the explanation.

Actually, I forgot to mention that the other similar project which I mentioned above has only 1 single LMK04828. 

In this case, I need at any power on time, my O/P's of LMK to be in phase and not be with the I/P ref clock.  

(Because, as u mentioned SYSREF can take any phase, but as I have a single device, I can be assured that SYSREF can be in one of the phases at one single time)

If my System/Project has multiple LMKs, then all the ZDM rules must & should be taken care of.  

Please correct me, If I am wrong. 

Hi Derek,

For the above design, I won't be using any Sync, I will just use SYSREF DIV as F/B to PLL1 in ZDM but my I/P ref clock (CLKIN0) is independent of SYREF.

i.e. Only 2nd rule of ZDM is followed

Please correct me.  

Hi Shekhar,

When you program the device, the divider state is effectively random. Nothing about the zero-delay rules will guarantee phase alignment between any of the device clocks and SYSREF on the same device - it just guarantees a relationship between the SYSREFs running on multiple devices with the same input clock phase. The big benefit of using the ZDM config with the SYSREF in the feedback path is that the SYSREF can also re-time SYNC pulses to a precise VCO clock cycle, without any complicated timing for the user. This SYNC could even be generated entirely in software, by toggling the SYNC_POL bit, or by triggering the SYNC off of lock detect using SYNC_PLLx_DLD bits. But one way or another, the output dividers need to have their phase relationship established with a phase sync, no matter what. This is also true for the multi-device scheme.

The benefit of following the ZDM rules in the multi-device scheme is:

• Since GCD(outputs, inputs) = input, there is only one possible isochronous phase for every PLL's phase detector
• Since the SYSREF divider is in the feedback path, there is only one possible phase for every SYSREF in the system
• Since GCD(outputs) = SYSREF, all device clocks can share an edge with the SYSREF edge (or be delayed an arbitrary amount from the SYSREF edge)
• Since the SYSREF can re-time SYNC events, every device can re-time an asynchronous SYNC pulse to align all device clock dividers to the SYSREF divider, and therefore to each other, across all devices

If you only have one device, and that device doesn't need to have a reproducible input-to-output phase relationship, there isn't really a reason you would have to follow the ZDM rules for reproducible phase relationships. You could just introduce an arbitrarily-timed software SYNC and set the device clocks/SYSREF phase relationship that way. The key benefit of the ZDM rules is that they establish a guaranteed way to produce an isochronous SYNC event on multiple device by meeting setup/hold time to a SYSREF clock running in the low MHz range, as opposed to a VCO running in the GHz range. When all you need is for all outputs on a single device to have a reproducible phase relationship, ZDM is superfluous - just SYNC to set the phase relationship, and you're done.

Does this make sense?

Regards,

Derek Payne

Hi Derek

So we shall be only toggling "SYNC_POL" bit via Software and expect SDCLK and DCLK be in phase irrespective of I/P Ref CLK. 

I am leaving SYNC or CLKIN0 pin as No Connection. 

So for below Req of 

1) SYSREF = 5.625MHz

2) DCLK = 112.5MHz

Both these CLK OUT need to be in phase

I am using below configuration

CLKIN1 = 5MHz

PDF1 = 0.625MHz

VCXO = 225MHz

PDF1 = 112.5MHz

VCO0 = 2475MHz

FB_MUX = SYSREF_DIV

PLL1 N CLK MUX = FB_MUX

Hi Derek,

Thank you for the detailed explanation. I am assuming that my queries have been resolved. Below are the conclusive points

• Single Device System
  • Case1: Input-Output non Phase Determinism
    • Work LMK in Dual Loop only 
    • No need to follow any rules of ZDM
      • The input clock is not a multiple of the SYSREF
      • PLL-R and PLL-N divider can be other than '1'
    • GCD(outputs) = SYSREF, all device clocks can share an edge with the SYSREF edge 
      • But mandate to use the "SYNC DIVIDERS" feature of TICS PRO
        • This will stop all SYNC inputs, set normal SYNC mode, enable all dividers for SYNC, issue a SYNC by
          toggling SYNC_POL, set all dividers to ignore SYNC, then return any other changed parameter to its
          original state
    • DONE
  • Case2: Input-Output Phase Determinism
    • Work LMK in Nested Zero-Delay Dual-Loop Mode
    • Follow both the rules of ZDM
      • Input Clock = SYSREF
      • SYSREF DIV as feedback
    • GCD(outputs) = SYSREF, all device clocks can share an edge with the SYSREF edge 
      • But mandate to use the "SYNC DIVIDERS" feature of TICS PRO
        • This will stop all SYNC inputs, set normal SYNC mode, enable all dividers for SYNC, issue a SYNC by
          toggling SYNC_POL, set all dividers to ignore SYNC, then return any other changed parameter to its
          original state
    • DONE
• Multi-Device System
  • Case1: Not a requirement
  • Case2: Input-Output Phase Determinism
    • Work LMK in Nested Zero-Delay Dual-Loop Mode
    • Follow both the rules of ZDM
      • Input Clock = SYSREF
        • If the input clock is a multiple of the SYSREF, N/R is not an integer
          • Then I have multiple phase relationship b/w input and output
            • I will use reset R-divider (LMK04832) which will match with one phase w.r.t. input (Phase Certainty) 
              • Should this reset be used at once together across all Devices?
      • SYSREF DIV as feedback
    • GCD(outputs) = SYSREF, all device clocks can share an edge with the SYSREF edge 
      • But mandate to use the "SYNC DIVIDERS" feature of TICS PRO
        • This will stop all SYNC inputs, set normal SYNC mode, enable all dividers for SYNC, issue a SYNC by
          toggling SYNC_POL, set all dividers to ignore SYNC, then return any other changed parameter to its
          original state
      • Should SYNC be done at once for all the devices?
    • All the Devices should receive an Input clock at the same time
      • I don't think different external VCXO on different devices create any phase issue?
    • DONE

Queries: 

• Should the "Digital delays" be configured other than default values only if we have routing issues for DCLK and SDCLK?
  • Why because, doesn't configuring SYNC Dividers make sure all device clocks can share an edge with the SYSREF edge?

Shekhar,

Very comprehensive summary. I agree with everything you have summarized for the single-device cases. As for the multi-device cases:

• In cases where R-divider reset is required, it is easiest to issue the R-divider reset simultaneously. It is technically possible to issue the reset on one device at a time, and manually match the R-divider phase by counting input cycles... but this is more trouble than just issuing a simultaneous reset to all devices. The setup time constraints for the R-divider reset to PLL1 are about 3-5ns for SYNC pin or about 150ps for CLKin0. 
• You do not have to issue the output divider SYNC all at once for the multi-device system. As long as you re-time the SYNC event to the SYSREF divider edge by setting SYSREF_MUX=1, and assert the SYNC signal for at least one full SYSREF divider period (+ setup time of 3-5ns for SYNC pin, or 150ps for CLKin0), the output divider reset will yield reproducible and isochronous clocks across all devices even if the SYNC is not simultaneous on all devices.
• In all of these cases, external VCXO phase does not impact operation at all.

The digital delays for DCLK and SCLK determine the number of VCO cycles after the SYNC event that will be swallowed before the clock begins. It is not correct that performing the "SYNC Dividers" function in TICS Pro will automatically guarantee device clock to SYSREF alignment. It is more accurate to say: there always exists settings for the DCLK/SCLK digital delays and global SYSREF delay, which ensure that device clocks and SYSREFs share an edge after a SYNC event. But the settings for digital delay are different for different divide values, and must be calculated beforehand. Default digital delay values are usually incorrect, because default digital delay values are selected for default divider values. Additionally, you don't always want device clocks and SYSREFs to share an edge; for instance, in many systems, the setup and hold window for SYSREF centers around the falling edge of the device clock instead.

Datasheet section 8.3.5 SYSREF to Device Clock Alignment gives an equation which can be used to pre-compute the SYSREF to Device Clock Alignment for any given device clock, using the DCLK/SYSREF divider values, the duty cycle correction for the DCLK, and the digital delays.

Regards,

Derek Payne

Hi Derek,

Thank you for the explanation. 

We have below queries

1. Both R-divider reset and output divider SYNC is driven on either the "SYNC" or "CLKIN0" pin.
   1. As R-divider reset needs to be simultaneous, means we have to drive this to all LMK devices at once
      1. This means this signal is length matched, which implies SYNC signal arrives at each device at once
         1. Hence the output divider SYNC also will simultaneously do happen to all devices?
2. When we carry out R-divider reset via SYNC pin, which registers to set?
   1. I meant because this pin does multiple functionalities, how after giving R-divider reset, it switches to o/p divider SYNC functionality? 
3. How exactly output divider SYNC is being carried out?
   1.  Why because when we carry out SYNC, what is the stage of SYSREF_MUX?
   2. How is this SYNC going to DCLK_divider reset?
   3. How is this SYNC going to SDCLK_divider reset?
      1. Please provide a diagram for this routing.
   4. 
4. We have a little less understanding of how SYNC makes DCLK and SDCLK divider in SYNC 

Hi Shekhar,

1. Usually the R-divider reset is at a very low frequency <10MHz, so it's not hard to make a divider SYNC that propagates across all devices simultaneously at such a low frequency. In theory the length matching required to make simultaneous R-divider SYNC could also be used to ensure simultaneous output divider SYNC, but then there are two challenging problems:
   1. One way to SYNC output dividers is through CLKin0, but you must re-time to the exact same VCO cycle on all devices. This means you must meet a setup time requirement of a few hundred picoseconds, across some unknown length-matching, between multiple devices. This is possible, but challenging.
   2. The other way to SYNC output dividers is through SYNC pin, which also gets re-timed to the VCO. But due to CMOS variability in the SYNC pin path, there is 3-5ns uncertainty in the SYNC pin timing, which makes directly SYNCing output dividers through SYNC pin almost impossible without re-timing to a slower, more consistent signal - such as the SYSREF divider. The SYSREF divider re-timing forms the core of every suggestion made so far, because it relaxes the SYNC window from "a single VCO cycle" to "a single SYSREF divider cycle". And furthermore, if the ZDM rules are followed, the SYNC can be any SYSREF divider cycle, since the SYSREFs of all devices will be in phase.
2. Datasheet section 8.3.1.1 describes the PLL1 R-divider synchronization sequence in detail. Since you are in nested ZDM, the phase of PLL2 R-divider is inconsequential.
3. ...
   1. For output divider SYNC, SYSREF_MUX is set to 1 (re-timed SYSREF).
   2. The SYSREF distribution path is also the SYNC path. The output of the SYSREF_MUX can be used as the internal divider reset signal. There are some bits, SYNC_DISx and SYNC_DISSYSREF, which gate the SYSREF distribution path to the divider reset for each channel. If these bits are set, the divider reset is gated and the SYSREF distribution path signal does not reset the divider. If these bits are cleared, the divider reset is ungated and the SYSREF distribution path signal will reset the divider on a HIGH signal.
   3. There's two components to a SYSREF reset:
      1. The main SYSREF divider functions just like a bigger output divider: it can be reset by the signal out of the SYSREF distribution path and the reset is gated by SYNC_DISSYSREF bit. If you are following the ZDM rules, there is no need to ever reset the SYSREF divider, because the SYSREF divider is always in phase across all devices. But when you need to set the phase of a single device, irrespective of input clock, you can reset the SYSREF divider so that both CLKOUT and SYSREF phases are reset.
      2. The local SCLKX_Y_DDLY is reset by setting SYSREF_CLR=1 for at least 15 VCO cycles. Incidentally, you could write SPI to the device at the maximum speed merely toggling SYSREF_CLR state 0->1->0 and this should always be sufficient for clearing SCLKX_Y_DDLY state.
   4. I have included two diagrams below: one clarifies the path when performing the SYNC and setting SYNC_DISx=0; one clarifies the path when enabling the SYSREF divider for continuous operation (as an example, could also be pulsed or some other value), with SYNC_DISx=1.

SYNC path, assuming SYNC pin or SYNC_POL toggle, using SYSREF_MUX = re-timed SYSREF divider while following ZDM rules:

SYSREF path, after synchronization is complete, using SYSREF_MUX = continuous SYSREF:

Regards,

Derek Payne