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LMX2820EVM: Reference input bandwidth when locked (i.e. 'hold' range over which PLL can follow the reference input frequency)

Part Number: LMX2820EVM
Other Parts Discussed in Thread: LMX2820, LMX2492

Good afternoon

We're looking at implementing the LMX2820 in a ramp generator system and I'd like to program the LMX2820 to a fixed centre frequency and then ramp the reference input frequency so that the PLL follows the reference input without reprogramming/calibrating the PLL/VCO.

Various measurements at different frequencies indicates the PLL can 'hold' lock to the reference input frequency from between a few MHz to 50MHz depending on settings.

Can someone tell me what the parameters are that have an impact on the hold range of the PLL over the reference input frequency please?

The implementation is to set a particular reference frequency generated by a DDS and then to lock the LMX2820 to this reference input and a particular RF output.  The DDS reference frequency will then be tuned over a 50MHz range with the ramp translated onto the VCO.  I am using PFDin with a feedback mixer for low phase noise.

I've read various control theory and PLL tech notes but can't find anything relating the PLL transfer function (including loop filter) to the reference input bandwidth.  I did initially think it may be related to the loop filter bandwidth but increasing and decreasing the LBW didn't make much difference to the hold range.

Many thanks and I look forward to hearing from you

Best regards

Jon

  • Hi Jon,

    Assuming you are using a 100MHz reference clock to lock LMX2820 to 5500MHz. Then the input/output frequency ratio is 55.

    If you alternate the reference clock by 50MHz, then the VCO will have to alternate by 50MHz x 55 = 2750MHz. This is not possible with any integrated VCO synthesizer in the market. Remember we have 7 VCO cores to take care 5500MHz tuning range. So each VCO core can support less than 1GHz tuning range. Furthermore, each VCO core is divided into over 100 sub-bands. As such, the actual tuning range, without a re-calibration to the VCO, will be around or less than 100MHz.

  • Hi Noel

    Many thanks for your reply, that does help but I have some more detailed questions and I was wondering whether there was someone within Texas Instruments I could chat with directly rather than posting on an open forum?

    For example I would be interested to know exactly how many sub-bands, how wide they are and whether they vary with temperature and/or device.  It would be helpful if we could centre our target frequency close to the centre of the sub-bands to reduce variability.

    Does it make a difference if we use an external feedback mixer so that the Fo/Fi ratio is 1 (or does that not make any difference as the calibration occurs using the internal N divider)?

    If I have understood your answer correctly too, this might improve if we were to use an external VCO?  

    Many thanks

    Jon

  • Hi Jonathan,

    What is your ramp range requirement from the synthesizer? If it is over 100MHz, I am sure you are not able to get linear ramp from the synthesizer, no matter which VCO core or sub-band is selected.

    If you make fo/fi = 1, then the output ramp range will also be equal to the input ramp range. You can use the Offset mixing with PFDIN pin function to make "N divider" = 1, then fo/fi will virtually become 1.

    If you consider to use external VCO, you may consider LMX2492, which is a PLL only device but it supports frequency ramp function. 

  • Hi Noel

    The ramp range requirement for the synth is about 50MHz but I've only been able to get about 35MHz out of the synth.  Also although the ramp width of 35MHz is fairly consistent, there it is variable how 'centred' the ramp is on the reference centre frequency.  I can recentre the ramp on the calibrated VCO frequency by manually forcing the capacitor values but I'm concerned this isn't suitable for our application.

    I am using the offset mixing feature using the PFDIN function.

    Thanks for the suggestion of the LMX2492, it does not meet our phase noise requirements on its figures of merit, plus is also a fractional-N synth and I would be concerned over the spurs for our application.

    It would be very helpful to speak with somebody in TI directly as for the reasons mentioned as I would like to discuss the finer points of our system requirements.

    Thanks and best regards

    Jon

  • Hi Jon,

    I will shoot you a mail, let's close this post by now.