Other Parts Discussed in Thread: ADC3244, DATACONVERTERPRO-SW
Hi team,
Please help to answer the following questions about ADC3244E evaluation board:
1. The maximum sampling rate of ADC3244E is 125msps, and the estimated total transmission rate should be 2gbps. It supports serial LVDS interface, but it is found that the upper limit of serial LVDS interface rate is 1.0gbps, which is less than 2gbps. Will it affect data transmission?
2. Can ADC3244E evaluation board be connected with FPGA development board supporting LVDS interface? Is there a relevant interface? Please elaborate.
3. The data transmission of ADC3244E evaluation board is (1) real-time transmission? Or (2) cache the collected data in the register of ADC evaluation board, and then transfer the cached data out at a certain rate?
4. For different ADCs, there are different interface types. What are the differences among LVDS, parallel LVDS, serial LVDS, DDR LVDS and QDR LVDS?
Thanks a lot.
Best regards,