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ADS1672: Relation between SCLK and master clock

Part Number: ADS1672

Hi team,

 

Here is the inquires from customer.

 

  1. They would like to use 3.3V at DVDD to communicate with FPGA I/O. Are there any concern if DVDD is a little bit over 3.3V ?
  2. In case of CLK input (master clock) at 20MHz and SCLK_SEL=’0’, SCLK is same as CLK input at 20MHz even if both /LVDS=’0’ and ‘1’.
    Referring the datasheet, SCLK should be same with CLK input (master clock)

    (Background)
    They will use 625ksps sampling rate and would like to know the interface should be LVDS or CMOS. (The length between FPGA and ADS1672 is several 10mm)
  3. According to datasheet, the clock amplitude should be equal to AVDD. It means that 5V amplitude clock source driving AVDD at 5V is needed ?

 

Thank you and best regards,

Michiaki

  • Hello Michiaki,

    1.  Yes, the ADS1672 can operate with DVDD=3.3V.  There might be a slight increase in digital noise coupling into the inputs at the higher DVDD voltage, but this also depends on the edge rate of the digital inputs and the capacitive loading on the digital outputs.  If DVDD exceeds 3.3V and is less than 3.6V (ABS MAX) the part will not sustain damage, but we do not have any data to predict performance in this range.

    2.  YES, if SCLK_SEL=0, then Fsclk=Fclk.  This is true if output is CMOS or LVDS.  With the lower clock speed of SCLK=20MHz, they can use either CMOS or LVDS for reliable communications.  If the distance between ADC and FPGA is less than 10cm, then I would suggest to use single CMOS line to reduce number of pins on FPGA.  However, if the FPGA supports LVDS, they may see lower noise using LVDS since they are operating with DVDD=3.3V.

    3.  YES, 5V amplitude for CLK is required.  There is no internal voltage level translation between the CLK circuit and the DVDD supply.  Either use a 5V clock oscillator, or use a voltage level translator.

    Regards,
    Keith Nicholas
    Precision ADC Applications