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ADS1672: Duty cycle and allowance jitter

Part Number: ADS1672

Hi team,

 

We got inquires from customer as following.

 

  1. Duty cycle of CLK
    In case of multiple conversion, customer will configure ADS1672 CLK = 20MHz, FastResponse, LowLatency, DR=625ksps.
    According to the datasheet, the duty cycle of CLK should be very close to 50% while min, max shows 45% and 55% in timing requirements.
    Is it enough min 45% and 55% ? If no, could share the target number ?
  2. The target number for clock jitter
    In case of configuration CLK=20MHz, FastResponse, LowLatency, DR=625ksps and maximized SNR between 600Hz and 60kHz, customer would like to know the target number of clock jitter.
    Or it would helpful if we can share the figure such as Figure 2. SNR plots for oversampling ADCs(a) or the data such as table 1. which shows between clock jitter, SNR and frequency. Could you share the such data for clock jitter ? Customer is worried about the degrading SNR performance by increasing jitter.

 

Thank you and best regards,

Michiaki

  • Hello Michiaki,

    1.  The ADS1672 will meet full datasheet performance with CLK duty cycle from 45% to 55%.

    2.  Maximum clock jitter can be calculated using the following equation:

    With data rate set to 625ksps, OSR=32.  The dynamic range at OSR=32 for the ADC is 107.5dB.  This is the internal thermal noise limit of the ADC.  Clock jitter will add additional noise.  In order to limit this additional noise to a small percentage of the thermal noise, we will set the DR limit for the jitter calculation to be 107.5+10dB, or 117.5dB.  Per above requirements, the maximum input frequency will be 60kHz.  

    OSR=32

    DR=117.5dB

    Fin=60kHz

    T-jitter = [sqrt(32)*10^(-117.5/20)]/[2*3.14*60000] = 20ps

    Regards,
    Keith Nicholas
    Precision ADC Applications