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Hello,
Need your help to review the schematic.
1) The application is for measure voltage from u0adc_in or u1adc_in from -100V to 100V. This application is likely an oscilloscope.
2) Sample rate of adc is 50M/s
3) U18 is LVDS clock powered by 3.3V, will it damage or impact the ADS4222 clock input (1.8V)?
4) FPGA data bus d0....d11 is connected to FPGA, is it ok with current in serial resistor?
5) Please comments on whole schematic.
Xiaoqiang,
The schematic looks fine. U18 output is LVDS so this should not be a problem.
Serial resistors are fine. If there is to much ringing on the data and or clock lines, you could increase these resistors to 22 Ohms.
Make sure the full-scale differential input on each input pin (INP and INM) swings symmetrically no more than VCM + 0.5V and VCM – 0.5V, resulting in a max 2VPP differential input swing.
Regards,
Jim