Hello,
We are debugging DAC38RF85 and Zynq7045, and we try to send 1990Mhz signal, LMFSHd=22210.
We use the internal PLL mode, and input clock is 2200Mhz, internal PLL locked to 5500Mhz. Now it can measure the clock frequency at CLK_TX port by divider 4, it indicates that PLL work normally.
As to the 204B interface, sync has detected by Vivado ILA, so the interface is also normal.(CGS and ILAS has improved, sync is high).
Now it could send single tone signal by configure 0x12F and 0x130, but when turn off the SPIDAC test, DAC has no output. In addition, all the alarm registers are masked, and turned off all the registers which may clear the output data of JESD block. But it could still test the output waveform. Could you please help to analyze?
Best regards
Kailyn
