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ADC12DJ3200: 8 lanes data output on ADC12DJ3200

jimmy xu1
Intellectual 490 points
Part Number: ADC12DJ3200

Two questions:

1). If 8 lanes data output on ADC12DJ3200 is selected, is it correct to select DA0+/- to DA7+/- for data output and leave DB0+/- to DB7+/- unconnected?

2) In TI ADC12DJ3200 reference design (DOC Title HSP001) schematic, there is no 100 ohm differential termination resistor there. But the data sheet tells there should be 100 ohm differential termination resistor for each data lane. Could we understand that in your FPGA board, there is 100 ohm termination resistor there, or there is internal 100 ohm inside in FPGA chip?

Thanks,

Jimmy

  • 0
    TI__Intellectual 1950 points

    Hi Jimmy,

    Section "7.4.3.1 JESD204B Output Data Formats" will give you more detail on which lanes to select since it's jmode dependent. For termination, depends on the FPGA used. Some will provide termination and others will not therefore,  I'd recommend checking the FPGA you are using to see if it has internal termination. This would help to simplify your board design.