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ADS5562: Verification Strategy of a two different Signal processing chains in an FPGA

Hari kumar
Prodigy 20 points
Part Number: ADS5562

 I have two ADC interfaces(ADS5562 and ADc4128) with FPGA and 32-bit processed output data from FPGA.
I have an IO signals to verify the Inputs and Outputs of FPGA.

But I don't have any test points to verify the intermediate output blocks of the design like mixer and filter. Since I need to cross check the functionality of mixer and filter also either its meeting my requirement or not. What is best method to evaluate the functionality of complete blocks along with intermediate blocks.

FPGA IO Diagram

 

I have following doubts with respect to the above block diagram.
1. Either I am doing right or Is there any best solution to verify the intermediate blocks of design along with actual IOs. Actual blocks of the design is mentioned in the attached figure.

2. If I have a 40K samples its very difficult to fed either in simulation or On-board testing, how to give this huge samples as part of simulation or ON-board Testing ?

3. what is the Idle way to verify the Signal processing chain in Simulation and On-board testing.

4. How to verify the build in test operation of ADS5562. Since it doesn't have any SPI read operation support.

  • 0
    TI__Mastermind 20365 points

    Hi Hari,

    It seems these questions are directed more about the FPGA in the system rather than the data converters, but we will try our best. Just note that you will likely get a better response for the FPGA questions from the FPGA manufacturer's help forum. A few suggestions we were able to round up:

    • Design a ‘bypass’ mode for the blocks, so if there is an intermediate point of interest, all the processing/filtering after that point should be bypassed so the output is fed straight to the I/Os.
    • To test the signal processing in simulation, one approach will be to remove the ADC from the picture completely:
      • Create a buffer of samples, feed it into the processing path, and finally capture the intermediate and outputs in different buffers.
      • Generate 'expected' output buffers using Matlab
      • Compare the two buffers
    • The above approach can be taken to FPGA by replacing the sample buffer with RAMs, and then using the various bypass modes to see the output at the I/Os

    Regarding question 4: Once the desired test pattern is chosen, write the appropriate bits to register 0x65 and verify the output of the data converter matches the selected test mode. (Ex. Ramp pattern -> write to register 0x65 value 0x80)

    Regards