The TI E2E™ design support forums will undergo maintenance from Sept. 28 to Oct. 2. If you need design support during this time, contact your TI representative or open a new support request with our customer support center.

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC3683: Operations without frequency locked DCLKIN

Part Number: ADC3683
Other Parts Discussed in Thread: CDCE6214

Hi,

the data sheet of the adc3683 states that the dclkin clock needs to be frequency locked to the sample clock.

I have an application where I don't have equidistant sampling points and hence cannot establish a frequency lock between the sample clock and dclkin.

Is such a mode of opperation possible with the adc3683, if so what are the requirements for dclkin.

Kind regards

Robert Braunschweiger

  • Hi Robert,

    Yes, the sample clock and DCLKIN must be frequency aligned/synchronous. In this instance, the phase relationship is not critical as the phase will be aligned inside of the ADC3683, but if the frequencies are not source synchronous/locked, then a bit slip will almost certainly occur.

    The most ideal solution would be to use the sample clock as a reference to an FPGA/Processor, and then create the 4.5x DCLKIN based off of the sample clock.

    Another solution is to use a PLL IC that can create a 4.5x output (TI has many options, like the CDCE6214).

    Best Regards,

    Dan