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ADS124S08: Timeout reset detection by FPGA?

Part Number: ADS124S08

Hello team,

I have a question about serial interface timeout feature of ADS124S08.

Is there any way for FPGA to know when ADC issues timeout SPI reset?

Best regards,

  • Hi Sato-san,

    The short answer is no.  There is no indicator or pin response that shows the timeout has occurred and the SPI has timed out.  The best action is to use CS which will reset the SPI internals of the ADS124S08 when CS goes high.  The timeout feature is for those customers that hold CS low continuously (or connect to GND).

    To use the timeout feature the register setting must first be set by setting bit 2 high in the SYS register.  If an incomplete byte transfer has not taken place within 2^15 tclk periods, the SPI bus will reset.  So one method for the FPGA is to wait 2^15 tclk periods after the last attempt for communication before starting a new communication.

    As you can see, using CS has a great advantage over relying on the timeout.  The timeout feature was added for those customers using isolation that want to limit the number of isolated communication signals.

    Best regards,

    Bob B