I'd like to know about Power-On-Reset described on page 22.
The data sheet says that " To make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms."
Is there anything else I need to do to meet this requirement other than having a bypass capacitor?
I plan to connect 0.1uF and 1uF capacitors to Vdd with reference to the evaluation board.
If this POR condition is not met, can it be replaced by a soft reset?
