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AMC3336: Min, max, and intermittent clocking

Erik Friesen
Prodigy 200 points
Part Number: AMC3336

What are the ramifications of slow clocking ( <9mhz)? Or perhaps, what happens with intermittent clocking, like if this was placed on an spi bus, or otherwise driven only when requiring an adc sample?


Also, for low sample rates, is there some prohibitive reason this can’t be done in C with some standard mcu?

  • 0
    TI__Mastermind 22950 points

    Hi Erik,

    A modulating clock would cause some data loss. If the clock starts and stops, you can have discontinuity in the output data assuming the data is still changing. If the input data stops with the clock, then you may have some contiguous data. 

    A filter can be done in C but some bit-banging would need to be done and would be rather difficult and time consuming to achieve. In this case, it's better to have a dedicated filter module or to use an FPGA to realize the filter. This is the most effective way to deal with the modulator bitstream. 

    Regards,

    Aaron Estrada

  • 0
    Prodigy 200 points

    I understand the data loss, but is there some minimum cycle count to bring up the subsystem? I’m assuming that the device borrows the clock for internal use or housekeeping? 

  • 0 in reply to Erik Friesen
    TI__Mastermind 22950 points

    Hi Erik,

    Just looking figure 6-2 in the data sheet, there are some clock cycles provided as VDD is brought up. There is a tstart time requirement based on VDD and I am unsure if there is any specific clock cycle requirement. I would play it safe here and follow the tstart typical timing of 0.6ms. 

    Regards,
    Aaron Estrada