• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 95 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC38RF89EVM: GUI parameter question

Kazuki Itoh
Genius 9425 points
Part Number: DAC38RF89EVM

Hi team,

Does  "Current Serdes Lane Rate" on the quick start page in DAC38RFxx EVM GUI mean the JESD data rate per lane?

My customer would like to check it so they can correctly configure parameters on FPGA IP setting.

Regards,

Itoh 

  • +1
    TI__Guru 67944 points

    Hi Itoh-san,

    The current SerDes lane rate is the physical data transfer rate from the FPGA to the DAC. It is the rate that had been 8b/10b encoded.

    The customer may refer to this information to configure the PHY layer (physical layer setting). For example, on the Xilinx Vivado tool, they will need to configure the GTH, GTY, etc configuration to fit the lane rate speed.

    -Kang