AFE5832: CONFIGURATION AFE5832

I debug the AFE5832, and found some issues.

1) FCLK can be decode stable under SYNC MODE and DESKEW MODE， but not under RAMP MODE or NORMAL MODE。

And it‘s the same at MED1426_REV1P1 board, so i think the problem maybe configuration via spi .

2) By the way I found that the 1.8V current under SYNC MODE is larger than NORMAL and RAMP MODE.

The power up sequence I shows below, i appreciate that  who can help me to check it.

(1) Set a reset signal (period about 100ns) after power on

 (2) wait 100ns, than set register via spi interface,

         step#1 spi_data <= 24'h00_0000;

          Must write 1

              step #2 spi_data <= 24'h03_0010;

              step #3 spi_data <= 24'hD1_0007;

             step #4 spi_data <= 24'hD4_0001;

          PLL reset

          wait for 100us

         step #5 spi_data <= 24'h41_8000;

         step #6 spi_data <= 24'h42_8000;

            wait for 10us

         step #7 spi_data <= 24'h41_0000;

         step #8 spi_data <= 24'h42_0000;

          init reg

         step #9  spi_data <= 24'h01_0000;

         step #10 spi_data <= 24'h04_0010;

          TR_TRIG for 3 ad clock

         step #11  spi_data <= 24'h03_0010;

           set skew mode

         step #12  spi_data <= 24'h02_0100;

           set sync mode

              step #13 spi_data <= 24'h02_0080;

              step #14 spi_data <= 24'h15_0009;

              step #15 spi_data <= 24'h21_0009;

              step #16 spi_data <= 24'h2D_0009;

              step #17 spi_data <= 24'h39_0009;

              step #18 spi_data <= 24'hC7_0000;

           set sync mode

              step #19 spi_data <= 24'h02_0380;

           set normal mode

              step #20 spi_data <= 24'h02_0000;

     (3) if need to change register after init procedure

         step #1 spi_data <=  24'h00_0000 or 24'h00_0010 ;(ADC or TGC reg)

         step #2 spi_data <=  register addr and value.