AFE5832EVM: Documentation + Interface/API

Hi Damian,

The output interface of AFE5832 device is LVDS Interface with a speed up to 1 Gbps. It consists of 16 differential data output lines and 2 Clk lines (total 18 differential pair).

You can refer to the timing diagram of the LVDS interface tp understand more about the system level requirements.

The data from the output of different channels are packed and placed in the serial LVDS interface which connects to the FPGA. The TSW1400 card has the FPGA ALTERA STRATIX IV with limited capabilities that are required to capture this data and deserialize it and decompress it and do further processing on it.

You can refer to section 8.3.12 LVDS Interface in the AFE5832 datasheet to understand more about the interface. Also read through the section 8.3.11 Serializer till the end to understand the different modes and data packing scheme.

So, in summary you may not need TSW1400 card but you will need to develop the data capture platform on any other FPGA capable of handling deserialization of the data from the LVDS interface and also adequate memory to store the same for further processing.

Thanks & regards,

Abhishek

Hi Abhishek,

Thank you for your response.

Could you please send me full datasheet for AFE5832?

I have been trying to get the full datasheet for the last 2 weeks but no success. I did request it on the website but no feedback.

I have only 11 pages available on the website but this documents says nothing about interface

My email: damian.lopata@orthoson.com

Best regards 

Damian

Hi Damien,

Let me get an approval to share the datasheet with you. I will reach you over mail soon. I assure you it wont take much time.

Thanks & regards,

Abhishek