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ADC3643EVM: Power up sequence of EVM

Ryuuichi machida
Guru 11645 points
Part Number: ADC3643EVM

Hello,

I would like you to confirm about below.

* According to schematic of EVM, REFBUF voltage come from AVDD via J16(Jamper 16).
However, it seems that input timing to AVDD pin and REFBUF pin is same.
According to datasheet 10 Initialization Set Up, TI described that min time b/w AVDD and REFBUF is 2ms.
So, it seems that EVM power up sequence is viorate this regulation.

Which one EVM setting and datasheet description is correct ?

BR,

  • 0
    TI__Genius 11831 points

    Hi Ryuuichi,

    I am checking into this and will get back to you soon.

    Regards, Amy

  • 0 in reply to Amy
    TI__Genius 11831 points

    Hi Ryuuichi,

    Can you clarify the mode you are planning to operate in?

    Internal or external reference? Differential or singled ended clock?

    Regards, Amy

  • 0 in reply to Amy
    Guru 11645 points

    Hello Amy-san,

    >Internal or external reference? Differential or singled ended clock?
    I would ask you about external reference with differential clock.

    BR,

  • 0 in reply to Ryuuichi machida
    Guru 11645 points

    Hello Amy-san,

    Do you have any update ?
    At first, I want to confirm whether datasheet description is correct for extenal supply(REFBUF, VREF) case or not.
    So, if you take more time to confirm whole question, please focus on above thing.


    BR

  • 0 in reply to Ryuuichi machida
    TI__Genius 11831 points

    Hi Ryuuichi,

    The datasheet description for external supply is correct, I would recommend referring to 1) Table 8-11 "REFBUF voltage levels control voltage reference selection" and 2) Section 8.3.3 Voltage Reference to understand how the REFBUF / VREF options function for this part.

    Thank you for your patience. I am still awaiting internal clarification on your question from the design team. I will get back to you soon with an update. 

    Regards, Amy

  • 0 in reply to Amy
    Guru 11645 points

    Hello Amy-san,

    Thank you for your reply.
    I re-read datasheet description and understood as shown below.

    --
    According to datasheet, if user do not use REFBUF to configure VREF setting, user can connect REFBUF to AVDD directly.
    => It seems that EVM apply this setting.

    On the other hand, there is following description and figure. If following description and figure can be applied for all use case, there is a contradiction.



    However, if user will configure VREF, clock and serial IF setting via SPI, this case is an exception.
    I think that above power sequence can be applied only if user will configure all device setting(not only VREF but also clk and serial IF) by using only REFBUF.
    How do you think ?

    BR,

  • 0 in reply to Ryuuichi machida
    TI__Genius 11831 points

    Hi Ryuuichi,

    These are good questions. I hope to get back with you by next week with clarification from the design team. I have reached out to them again with your additional feedback. 

    Regards, Amy

  • 0 in reply to Amy
    TI__Genius 11831 points

    Hi Ryuuichi,

    Here is the feedback I have received:

    If nothing is connected to the REFBUF pin (meaning that REFBUF is pulled up to VDDA through internal pull up resistor), then the default is external reference. There are no timing constraints on REFBUF in this case. Reference can be changed to internal reference with a SPI write.

    If the REFBUF pins needs to be set at some voltage, then the 2 ms interval will need to be followed after the VDDA bring up. In this case, the reference (internal or external) will be determined by the value of the REFBUF pin voltage. This can be overridden with SPI if needed.

    Regards, Amy

  • 0 in reply to Amy
    Guru 11645 points

    Hello Amy-san,

    Thank you for your reply.

    If nothing is connected to the REFBUF pin (meaning that REFBUF is pulled up to VDDA through internal pull up resistor), then the default is external reference. 

    For above case(REFBUF > 1.7V), it seems that  TI only allow user should input REFBUF by using AVDD not another 1.8V source.
    Is my understanding correct ?
    (What I want you to confirm is when REFBUF > 1.7V setting will be applied, user can not prepare two voltage source.)

    BR,

  • 0 in reply to Ryuuichi machida
    TI__Genius 11831 points

    Hi Ryuuichi,

    Our design team provided some feedback on this: 

    For a REFBUF voltage > 1.7 V, using either external reference or differential clock, the power-up timing should be the same as VDDA, or tied to VDDA. To clarify your question, there is no issue to use an external source as long as the power-up timing is the same as VDDA. 

    Regards, Amy

  • 0 in reply to Amy
    Guru 11645 points

    Hello Amy-san,

    Thank you for your reply.
    I understood that REFBUF and VREF can be powered up same timing as VDDA in case of "REFBUF > 1.7V". 
    However, I think we can not understand this only by reading datasheet, so do you have plan to clarify this point in future datasheet ?

    BR,

  • +1 in reply to Ryuuichi machida
    TI__Genius 11831 points

    Hi Ryuuichi,

    I have looped our systems engineer in and we are currently working on updating the datasheet to bring more clarity on this topic. Thank you for letting us know about the confusion, we appreciate the feedback.

    Regards, Amy