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TSW1400EVM: USER_LED3 OFF

Aymeric Guignard
Prodigy 10 points

Part Number: TSW1400EVM

Hello,

I am trying to test an ADC3243EVM with a TSW1400 board. After loading ADC324x_2W_14bit firmware and launching a capture, I'm getting "Clock from ADC EVM not received by FPGA board" message from HSDC Pro software.
Indeed, all LEDs of the TSW1400 are ON except USER_LED3 and USER_LED4.

I supply the TSW1400EVM (on port J12) by using a 5V 4A bench power supply, and ADC3243EVM (on port J15) with a 5V 3A power brick.

ADC3243EVM jumper connections are :
* JP1 -> 2,3
* JP2, JP3, JP4, JP5 -> closed
* JP6, JP7 -> 1,2

TSW1400 jumper connections are :
* JP3, JP4, JP8 -> 2,3
* JP5, JP6, JP7 -> closed

A 40 MHz, 0 dBm clock from a RF signal generator is provided to the ADC3243EVM port J9 (CLK). J1 (CHA) and J4 (CHB) ports are not connected.
The ADC3000 GUI isn't installed on my computer, I only use ADC3243EVM SW1 to reset the ADC3243 registers to default.

I already have checked the supply voltages of the 2 boards -> they seem fine.
I also measured DCLK and FCLK at the ADC3243EVM HSMC connector with differential probes. FCLK looks clean and locked at 20 MHz (fig 1). DCLK is also locked at 140 MHz, but seems less clean (fig 2).

Can someone tell me where my problem could come from ?

Thanks,

Aymeric

fig 1 : FCLK

fig 2 : DCLK

  • 0
    TI__Mastermind 20335 points

    Hi Aymeric, one of our experts is looking into this for you and will have feedback for you soon. Thanks

  • +1
    TI__Genius 12881 points

    HI Aymeric,

    Thank you for thoroughly checking into this and and sending along the captures. I set up the ADC3243 in the lab. User LED4 should remain off on the TSW1400 capture card, but User LED3 should come on once the capture card receives the FCLK and DCLK signals. Your jumper settings are all correct. The device should power up in a state ready to go without the need of the ADC3000 GUI. The SW reset you are doing is all that is required to ensure the part is set in default configuration.

    Since you have demonstrated that the clock signals are at the output of the FMC connector, my suspicion is that your capture card may have an issue. Try probing R54 on the TSW1400 (found on the backside of the board - TSW1400 schematic pg. 7). This is where the DCLK signal goes into the FGPA. Let us know what you find.

    Regards, Amy

  • 0 in reply to Amy
    Prodigy 10 points

    Hi,

    Thank you for your response. Now knowing that the problem don't come from the ADC, I focused on the TSW1400.
    Before call into question the board or the FPGA, I have just disconnected-reconnected the 2 cards and everything works fine now ! :)

    Regards,
    Aymeric

  • 0 in reply to Aymeric Guignard
    TI__Genius 12881 points

    Hi Aymeric,

    That is great news, glad to hear it is working. Please reach out if you have other questions.

    Regards, Amy