This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV2548-EP: Sample and hold structure

Part Number: TLV2548-EP
Other Parts Discussed in Thread: TLE2022, TLV2548

I am getting some unintended adjacent channel to channel coupling between an input channel of maximum input voltage (say 4.095V), and the adjacent channel of 0V.

The inputs to the ADC is driven by a TLE2022 configured as a follower, so the source impedance is relatively low.

While the datasheet specifies the Input MUX On Resistance at 500 ohms, and the input capacitance at 50pF (assumed to be sample and hold cap value), what is not specified is the resistance of the sample and hold switch.

Could someone provide a more detailed description of the input structure of this device so setting time can be analyzed ?  I have attached a small drawing showing my vision of this structure.

Thanks.

  • Hi Gregory,

    Your depiction above is essentially correct, the total input on resistance is the 500 ohms mentioned in the datasheet.  The issue you are describing sounds like a drive problem ahead of the ADC input.  The TLV2548 does not force the S/H cap to a fixed value between samples, so in the case you mention above, if CH0 is at 4.096V and CH1 is at 500mV, you could see some of the residual sample in the CH1 conversion results.  That being said, can you tell us what sampling method you are using (short, long or extended), what your SCLK speed is and finally what R/C values you might have in between the TLE2022 and the TLV2548? 

  • Hi Tom,

    Thank you for the reply. Here is more info on our system.

    The TLE2022 directly drives the A/D inputs of the TLV2548 without any RC filtering in between. The S/H is setup for "long" 24 SCLK cycles with an SCLK frequency of 8MHZ.

    Here is my analysis.

    (1/8MHZ) x 24 SCLK cycles = 3uS SH time.

    500 ohms x 50pF = 25nS tau.

    25nS x 9 tau settling to approx 1/2 LSB at 12 bits = 225nS minimum

    The numbers above assume that the TLE2022 has 0 ohms output impedance, but it doesn't. For the next analysis, we will assume a more reasonable number for the TLE2022's output impedance, let's say 200 ohms.

    200 Output impedance + 500 ohm input impedance = 700 ohms total.

    (700 ohms x 50pF) x 9 tau  = 315nS minimum assuming 200 ohm output impedance

    Actual S/H time is still much greater than is needed for our required accuracy (3uS >> 315nS)

    This leads me to believe that there is additional impedance in the input path that is unaccounted for.

    Any advice is appreciated.

    Thanks.

  • Hi Gregory,

    Please take a look at this video from our TI Precision Labs Series on ADC's.  It provides details on why the R/C is needed in front of SAR ADC's such as the TLV2548.  We also have an Analog Engineer's Calculator tool that includes a section on calculating the ADC SAR Drive components based on the input S/H cap and the sample time.  Here is a screen shot from that tool:

    Please try adding a 499ohm and 1nF cap between the TLE2022 and of one of your input channels to the TLV2548 and let me know if that improves the conversion results.

  • Hi Gregory!

    Have you made any headway with the sampling of the TLV2548?

  • Hi Tom,

    Thanks for the follow-up. Yes, adding the 499 ohm resistor and 1000pF cap between the TLE2022 op-amp and the ADC inputs as you suggested worked. Although I haven't checked the absolute accuracy yet, the ADC is behaving much better.

  • Happy to hear that!  Thank you for the feedback.