TI-JESD204-IP: connection to FPGA XA7Z030FBV484

Hi Mukuno-san,

Kindly help me with a few more details. When you say the IP does not work normally, what does that mean? I am listing a few possibilites:

1> Is the data incorrect?

2> Does the IP release lanes?

3> What is the value of the rx_sync_n output of the JESD IP?

Please let me know if the customer has updated the transceiver file to connect the CPLL related ports (instead of the QPLL).

Regards,

Ameet

Ameet-san,

They cannot find about 1, 2 and 3 on the tool of Xilinx, because ILA have shown "no clock" .

They tried to uninstall and re-install for Vivado/Xlinks.
However, it was not improved. they could not get cpll_locked signal.

They found the following codes in the gtx_8b10b_rxtx.sv.
Should they modify those codes to operate with CPLL?
How should they do to get the cpll_locked signal.

  // Following signals are dummy and tied to 0
  assign qpll1_locked = {NUM_QUADS{1'b0}};
  assign cpll_locked = {NUM_LANES{1'b0}};
  assign cdr_locked = {NUM_LANES{1'b0}};

Also , they have another question.

Do you have the IBIS model for ADC09SJ800?

we cannot find it on the ti.com.

Thanks

Muk

Hi Mukuno-san,

Yes, if they change the gtx transceiver from QPLL to CPLL, some of the ports will change, and they need to modify the code. It is also important that they run a simulation of the code (with the transceiver) to make sure that the reset FSM's complete correctly. The gtx_8b10b file included with the reference design is coded for a QPLL, which is why the other locked signals are tied to '0'. 

In addition, if the ILA is showing 'no clock' that means the logic that generates the clock to that ILA is not functioning. This may again be because they have switched to the CPLL.

I will check with Neeraj about the IBIS models.

Regards,

Ameet

Thanks Ameet-san

Do you have any update for IBIS model?

Muk

Hi Mukuno-san,

Since the conversation has been taken offline. I am closing the post. 

Regards,

Neeraj