Hi, Team:
When the input signal is greater than 0dbfs, the signal collected by FPGA becomes more spurious, like overflow.
I want to ask what is the maximum input signal allowed by adc34J44.
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Hi, Team:
When the input signal is greater than 0dbfs, the signal collected by FPGA becomes more spurious, like overflow.
I want to ask what is the maximum input signal allowed by adc34J44.
Hi Zhen,
The max input signal that the ADC should have is 2Vpp differential, see page 8 of the datasheet, otherwise, the signal is too large and will go above 0dBFS, in which case, the ADC is in an over-ranged condition.
Regards,
Rob
Hi Zhen,
Thank you for the picture. This helps.
Couple of questions and things to try.
Can you send me a picture of the FFT with a lower voltage?
In your test setup, sometimes the signal generator is 1.6Vpp, but it means RMS. So, the output could be much higher than expected.
Also, in your FFT, it looks like the sampling is off. Are you using a window function?
Are you coherently sampling or non-coherentely sampling? Here is a good article that describes the two differences:
Thanks,
Rob