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ADS127L11: RESET / SCLK timing for td(RSSC)

Yuto Kitamura
Expert 4600 points
Part Number: ADS127L11

Hi team,

I got question about RESET / SCLK timing for td(RSSC).

As shown in Figure 6-3 in D/S, do we need to keep SCLK "Low" while td(RSSC) timing?

Or td(RSSC) is just a time that the communication has not started, thus we can input the SCLK without any problems?

Best regards,

Yuto

  • 0
    TI__Mastermind 39640 points

    Hello Yuto-san,

    td(RSSC) is the delay time between the rising edge of /RESET and the first SCLK rising edge when /CS is low.  If /CS is held high after RESET, then you can have SCLK activity during this delay period.

    Figure 6-3 timing as shown assumes that /CS is held low, for example in 3-wire SPI mode.  If you are using 4-wire SPI, as long as /CS is high, then any SCLK activity will be ignored.  In 4-wire SPI mode, I suggest keeping /CS high after RESET for the td(RSSC) time period, and then take /CS low to start a SPI frame.

    Regards,
    Keith Nicholas
    Precision ADC Applications