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DAC3482: fsync equation and SYNC capture edge

Taketo Sato
Genius 9475 points
Part Number: DAC3482

Hello team,

I have two quick questions for DAC3482. Could you please confirm below?

  1. Datasheet equation 1 on p.32 is all same as equation 2. Is equation 1 correct? not "fsync = fdataclk / (n x 8)"?
  2. SYNCP/N is captured with rising edge of DATACLKP/N, similar to FRAMEP/N? or falling edge or DATACLKP/N?

Best regards,

  • +1
    TI__Guru 66114 points

    Hi Taketo-san,

    Taketo Sato said:
    Datasheet equation 1 on p.32 is all same as equation 2. Is equation 1 correct? not "fsync = fdataclk / (n x 8)"?

    Yes, this is correct for the FSYNC. The reason for the difference for FSYNC in byte wide mode vs Fostr is due to the internal FIFO digital design in byte wide mode. 

    Taketo Sato said:
    SYNCP/N is captured with rising edge of DATACLKP/N, similar to FRAMEP/N? or falling edge or DATACLKP/N?

    Yes, SYNCCP/N is captured with rising edge of DATACLKp/n, with the same setup/hold time requirement.

  • 0 in reply to Kang Hsia
    TI__Genius 9475 points

    Hello Hsia-san,

    Thank you for your comment.

    Could you let me know detail why fsync in byte wide mode can be "fsync = fdataclk / (n x 16)"?

    I thought Byte wide mode equation is representing repeating multiple 8 FIFO samples, n x 8, so why it cannot be "fsync = fdataclk / (n x 8)"?

    Best regards,

  • +1 in reply to Taketo Sato
    TI__Guru 66114 points

    Hi Taketo-san,

    In byte wide mode, the FIFO output clock is the DACCLK/interpolation

    the FIFO input clock is DATACLK. 

    Ideally, DATACLK should be the same as DACCLK/Interpolation.

    However, since it is byte wide mode, it takes two DATACLK cycles to complete one I/Q sample stream. This is the main reason that Fsync need additional factor of divide by 2 to rate match the FIFO output clock rate.